Motorola MVME162LX 300 Series Installation And Use Manual page 175

Table G-2. Mezzanine Connector J16 Interconnect Signals (Continued)
Pin Signal
Number Mnemonic
62 RDRAM_A8
63 GND
64 RDRAM_A9
65 DRAMCAS0*
66 DRAMRAS*
67 DRAMCAS1*
68 GND
69 DRAMCAS2*
70 DRAMOE0*
71 DRAMCAS3*
72 DRAMOE1*
73 GND
74 DRAMOE2*
75 DRAMWELL*
76 DRAMOE3*
77 SRAMWELL*
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Signal
Signal Name and Description
Direction
Input DRAM Address (bit 8). Parity DRAM
row/column address line.
Ground.
Input DRAM Address (bit 9). Parity DRAM
row/column address line.
Input DRAM Column Address Strobe (line 0).
Parity DRAM column address strobe.
Input DRAM Row Address Strobe. Parity
DRAM row address strobe.
Input DRAM Column Address Strobe (line 1).
Parity DRAM column address strobe.
Ground.
Input DRAM Column Address Strobe (line 2).
Parity DRAM column address strobe.
Input DRAM Output Enable (line 0). Parity
DRAM output enable signal.
Input DRAM Column Address Strobe (line 3).
Parity DRAM column address strobe.
Input DRAM Output Enable (line 1). Parity
DRAM output enable signal.
Ground.
Input DRAM Output Enable (line 2). Parity
DRAM output enable signal.
Input DRAM Write Enable (lines D07-D00).
Parity DRAM write enable signal.
Input DRAM Output Enable (line 3). Parity
DRAM output enable signal.
Input SRAM Write Enable (lines D07-D00).
Mezzanine Board Connectors
G
G-9