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IndustryPack Logic Interface Interconnections
Table I-1. IndustryPack Interconnect Signals (Continued)
Pin
Number
25, 26
27
28
29
30
31
I
32
33
34
I-2
Signal
Mnemonic
GND
Ground. Second and third of four ground pins. Serve as zero-
volt reference for logic signals, and as return path for the power
supplies furnishing operating voltages to the IndustryPack.
+5V
+5 Vdc Power. Second of two +5V pins. Primary supply for
digital logic functions on the IndustryPack.
R/W*
Read/Write. Indicates the direction of data movement on the
data bus. High indicates a read cycle (data lines driven by the
IP); low indicates a write cycle (data lines driven by the
MVME162).
IDSel*
IndustryPack ID. First of four ''select'' lines driven by the
MVME162 to enable the IP. This line is used to read a 32-byte
ROM containing the IP identification information. IDSel* is not
bussed; the signal is unique to each IndustryPack.
DMAReq0
DMA Request 0. One of two DMA request lines; driven by the
IndustryPack to indicate that the IP wishes to have a DMA cycle
performed on DMA channel 0.
MemSel*
Memory Select. Second of four ''select'' lines driven by the
MVME162 to enable the IP. This line is used in memory read or
write cycles. MemSel* is not bussed; the signal is unique to each
IndustryPack. An IP need not respond to MemSel* if it has no
memory.
DMAReq1
DMA Request 1. One of two DMA request lines; driven by the
IndustryPack to indicate that the IP wishes to have a DMA cycle
performed on DMA channel 1.
IntSel*
Interrupt Vector Select. Third of four ''select'' lines driven by
the MVME162 to enable the IP. This line is used in reading the
IP's interrupt vector during an interrupt acknowledge cycle.
IntSel* is not bussed; the signal is unique to each IndustryPack.
An IP need not respond to IntSel* if it has no interrupt requests
asserted.
DMAck*
DMA Acknowledge. This is driven by the controller and is used
to qualify a DMA cycle. It is bussed to the IP connectors.
Signal Name and Description
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