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Board Level Hardware Description
1
:
!
Caution
1-16
The battery backup function for the onboard SRAM is provided by a
Dallas DS1210S device that supports primary and secondary power
sources. In the event of a main board power failure, the DS1210S checks
power sources and switches to the source with the higher voltage.
If the voltage of the backup source is less than two volts, the DS1210S
blocks the second memory cycle; this allows software to provide an early
warning to avoid data loss. Because the second access may be blocked
during a power failure, software should do at least two accesses before
relying on the data.
The controller provides jumpers (on J13) that allow either power source of
the DS1210S to be connected to the VMEbus +5V STDBY pin or to one
cell of the onboard battery. For example, the primary system backup
source may be a battery connected to the VMEbus +5V STDBY pin and
the secondary source may be the onboard battery. If the system source
should fail or the board is removed from the chassis, the onboard battery
takes over.
Further details on SRAM configuration and specifics on SRAM
performance can be found in the section on the SRAM Memory Controller
in the MCchip Programming Model in the MVME162LX Embedded
Controller Programmer's Reference Guide. The SRAM arrays are not
parity protected.
For proper operation of the SRAM, some jumper
combination must be installed on the respective Backup
Power Source Select Header. Refer to the jumper
information in Chapter 2. If one of the jumpers is used to
select the battery, the battery must be installed on the
MVME162LX. The SRAM may malfunction if inputs to
the DS1210S are left unconnected.
The SRAM is controlled by the MCchip, and the access time is
programmable. Refer to the MCchip description in the MVME162LX
Embedded Controller Programmer's Reference Guide for additional
information.
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