Intel Agilex User Manual page 15

2. Intel Agilex Clocking and PLL Architecture and Features
UG-20216 | 2019.04.02
2.2.6.4. Normal Compensation Mode
An internal clock in normal compensation mode is phase-aligned to the input clock pin.
The external clock output pin has a phase delay relative to the clock input pin if
connected in this mode. The Intel Quartus Prime Timing Analyzer reports any phase
difference between the two. In normal compensation mode, the delay introduced by
the clock network is fully compensated. Only one output clock can be compensated in
normal compensation mode.
Figure 13. Example of Phase Relationship Between the PLL Clocks in Normal
Compensation Mode
The external clock output can
lead or lag the PLL internal
clock signals.
2.2.6.5. Zero-Delay Buffer Mode
In zero-delay buffer (ZDB) mode, the external clock output pin is phase-aligned with
the clock input pin for zero delay through the device.
In this mode, you must use the same I/O standard on the input clocks and clock
outputs to guarantee clock alignment at the input and output pins. You cannot use
differential I/O standards on the PLL clock input or output pins.
To ensure phase alignment between the
(
CLKOUT
bidirectional I/O pin serves as the feedback path connecting the
ports of the PLL. The bidirectional I/O pin must always be assigned a single-ended I/O
standard. The PLL uses this bidirectional I/O pin to mimic and compensate for the
output delay from the clock output port of the PLL to the external clock output pin.
Note: To avoid signal reflection when using ZDB mode, do not place board traces on the
bidirectional I/O pin.
Send Feedback
PLL Reference
Clock at the Input Pin
PLL Clock at the
Register Clock Port
Dedicated PLL
Clock Outputs
) pin in ZDB mode, instantiate a bidirectional I/O pin in the design. The
Phase Aligned
pin and the external clock output
clk
Intel
and
fbout fbin
® ™
Agilex Clocking and PLL User Guide
15