Intel Agilex User Manual page 13

2. Intel Agilex Clocking and PLL Architecture and Features
UG-20216 | 2019.04.02
Normal and source synchronous compensation modes compensate for the insertion
delay of a routed core clock. For Intel Agilex devices, you can achieve core clock
compensation by routing a dedicated feedback clock from the
to emulate the insertion delay of the compensated
Intel recommends the non-dedicated feedback mechanism because it uses the clock
resources most efficiently.
2.2.6.1. Direct Compensation Mode
In direct mode, the PLL does not compensate for any clock network delays. This mode
provides better jitter performance compared to other compensation modes because
the clock feedback into the phase frequency detector (PFD) passes through less
circuitry. Both the PLL internal- and external-clock outputs are phase-shifted with
respect to the PLL clock input.
Figure 10. Example of Phase Relationship Between the PLL Clocks in Direct Mode
The PLL clock outputs lag
the PLL input clocks
depending on routing
2.2.6.2. LVDS Compensation Mode
LVDS compensation mode maintains the same data and clock timing relationship seen
at the pins of the internal serializer/deserializer (SERDES) capture register, except that
the clock is inverted (180° phase shift). Thus, LVDS compensation mode ideally
compensates for the delay of the LVDS clock network, including the difference in delay
between the following two paths:
• Data pin-to-SERDES capture register
• Clock input pin-to-SERDES capture register
The output counter must provide the 180° phase shift.
Send Feedback
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port
delays.
External PLL
Clock Outputs
counter output clock network.
C
Phase Aligned
®
Intel Agilex
counter in the I/O PLL
M
™
Clocking and PLL User Guide
13