External Memory Interface; Asynchronous Sram Memc - Renesas R-IN32M3 Series User Manual

R-IN32M3 Series: Board design edition 11. External MCU/Memory Interface Pins
11.2

External Memory Interface

This section describes the connection as a master device to an external memory.
The operating connection mode of the external memory interface depends on the level of the signal on the MEMCSEL
pin (see Table 11.1).
11.2.1

Asynchronous SRAM MEMC

The asynchronous SRAM MEMC is externally connectable to paged ROM, ROM, SRAM, or peripheral devices with an
interface similar to the SRAM interface via a 16- or 32-bit bus.
The external MCU interfaces for the asynchronous SRAM MEMC and the synchronous method burst access MEMC are
multiplexed with each other. When both the MEMCSEL and MEMIFSEL pins are at the low level, the asynchronous
SRAM MEMC can be used.
When both the BOOT0 and BOOT1 pins are at the low level, booting up proceeds from the memory connected to CSZ0.
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Dec. 28, 2018