Pll Power Pins; Recommended Configuration Of Filter; Figure 4.1 Recommended Configuration Of Filter - Renesas R-IN32M3 Series User Manual

R-IN32M3 Series: Board design edition
4.

PLL Power Pins

The PLL circuit is susceptible to noise. To reduce the influence of noise, it is recommended to place filters in the power
supply pin of the PLL. Also if user avoid the interference noise of the PLL board and power supply, the usage of user
ferrite beads (FB).
4.1

Recommended Configuration of Filter

Figure 4.1 shows the recommended configuration of the filter for the PLL power supply pins.
VDD10（1.0V）

Figure 4.1 Recommended Configuration of Filter

Caution. Put C1 as close as possible to the PLL_VDD and PLL_GND pins.
C2 placement is less critical and there is no problem even if it can't be arranged as close to
the R-IN32M3 as C1.
R18UZ0021EJ0400
Dec. 28, 2018
FB
C2
FB
C1: 0.1-µF ceramic capacitor
C2: ≥ 4.7-µF capacitor
FB: Impedance: 600Ω@100 MHz / DC resistance component: 0.3Ω or below
Reference ferrite beads: TDK MPZ2012S601A, MPZ1608S601A
R-IN32M3
PLL_VDD
PLL
C1
PLL_GND
4. PLL Power Pins
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