Figure 11.9 Connection Example With 32-Bit Paged Rom (Asynchronous Sram Memc); Figure 11.10 Connection Example With 16-Bit Paged Rom (Asynchronous Sram Memc) - Renesas R-IN32M3 Series User Manual

R-IN32M3 Series: Board design edition
11.2.1.2 Connection Example with Paged ROM
The following figure shows an example when this LSI chip is connected to paged ROM.
R-IN32M3

Figure 11.9 Connection Example with 32-Bit Paged ROM (Asynchronous SRAM MEMC)

R-IN32M3

Figure 11.10 Connection Example with 16-Bit Paged ROM (Asynchronous SRAM MEMC)

Caution. The on-page mode of paged ROM is available only when the ROM is connected to CSZ0.
R18UZ0021EJ0400
Dec. 28, 2018
A2-A21
D16-D31
CSZ0
RDZ
WRSTB Z
D0-D15
A1-A20
D0-D15
CSZ0
RDZ
WRSTB Z
11. External MCU/Memory Interface Pins
A0-A19
O0-O15
Paged ROM
/CE
(1 Mword × 16 bits)
/OE
/WE
A0-A19
O0-O15
Paged ROM
/CE
(1 Mword × 16 bits)
/OE
/WE
A0-A19
O0-O15
Paged ROM
/CE
(1 Mword × 16 bits)
/OE
/WE
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