Figure 11.11 Connection Example With 32-Bit Sram (Synchronous Burst Access Memc); Figure 11.12 Connection Example With 16-Bit Sram (Synchronous Burst Access Memc) - Renesas R-IN32M3 Series User Manual

R-IN32M3 Series: Board design edition
11.2.2.1 Connection Example with SRAM
The following figure shows an example when this LSI chip is connected to SRAM.
R-IN32M3

Figure 11.11 Connection Example with 32-Bit SRAM (Synchronous Burst Access MEMC)

R-IN32M3

Figure 11.12 Connection Example with 16-Bit SRAM (Synchronous Burst Access MEMC)

Remark. n = 0 to 3
Note: When the "address/data multiplexing" feature is enabled (the ADMUXMODE pin is at the high
level), separate connection of the address bus is not required.
R18UZ0021EJ0400
Dec. 28, 2018
BUSCLK
Note
A2-A19
D16-D31
CSZn
RDZ
(WRZ3) / BENZ3
(WRZ2) / BENZ2
WRSTB Z
D0-D15
(WRZ1) / BENZ1
(WRZ0) / BENZ0
BUSCLK
Note
A1-A18
D0-D15
CSZn
RDZ
(WRZ1) / BENZ1
(WRZ0) / BENZ0
WRSTB Z
11. External MCU/Memory Interface Pins
BUSCLK
Note
A0-A17
I/O1-I/O16
SRAM
/CS
(256 Kwords × 16 bits)
/OE
/UB
/LB
/WE
BUSCLK
注
A0-A17
I/O1-I/O16
SRAM
/CS
(256 Kwords × 16 bits)
/OE
/UB
/LB
/WE
BUSCLK
Note
A0-A17
I/O1-I/O16
SRAM
/CS
(256 Kwords × 16 bits)
/OE
/UB
/LB
/WE
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