Renesas R-IN32M3 Series User Manual page 77

R-IN32M3 Series: Board design edition
Rev. Date
3.00 Feb. 28, 2017
R18UZ0021EJ0400
Dec. 28, 2018
Page
10 5.1 Built-in Regulator Used
Pin handling and the GND description in Figure 5.1 were modified. The description
on the capacitor substitution method was added.
11 5.1 Built-in Regulator Used
Table 5.1 was added to complement the list of the recommended parts.
12 5.2 Built-in Regulator Unused
Pin handling and the GND description in Figure 5.3 were modified.
13 6. GPIO Port Pins
The reference in separate user's manuals, modified
14 7. Ethernet PHY Pins (R-IN32M3-EC Only)
The description that this section was for the R-IN32M3-EC only was added to the
section title.
7.1 Ethernet PHY Power Supply Pins
Pin names of Rx/Tx analog power supply pins and the description of power supply
pins were modified.
15 7.2 100Base-TX Pins
Pin handling and the GND description in Figure 7.2 were modified. Remark and
Notes were moved to outside of the figure frame.
16 7.2 100Base-TX Pins
Pin handling and the GND description in Figure 7.3 were modified. Remark and
Notes were moved to outside of the figure frame.
7.2 100Base-TX Pins
Note was added to R1 to R6 in Table 7.1.
19 7.3 100Base-FX Pins (Optical Fiber)
Pin handling and the GND description in Figure 7.7 were modified. Remark was
moved to outside of the figure frame.
20 8. GMII Pins (R-IN32M3-CL Only)
Pin handling in Figure 8.1 was modified. Remark was moved to outside of the
figure frame.
21 8.2 Circuit Design around GMII
The description of the number for Ethernet ports was modified.
23 9. CC-Link Pins
Pin handling and the GND description in Figure 9.1 were modified. The name for
CC-Link clock pins was modified. Note 3 was added.
25 11. External MCU/Memory Interface Pins
As the mode setting pin, the ADMUXMODE pin was added. Note when accessing
the CC-Link IE field wad added.
27 11.1.1 Asynchronous SRAM Interface Mode
The description of pin handling in Figure 11.1 and Figure 11.2 was modified. The
position for the HBUSCLK pin and Note was modified.
29 11.1.2 Synchronous SRAM Interface Mode
The position for the HBUSCLK pin in Figure 11.3 and Figure 11.4 was modified.
30 11.1.3 Synchronous SRAM-Type Transfer Mode
The description of pin handling in Figure 11.5 and Figure 11.6 was modified. The
position for the HBUSCLK pin and Note was modified.
Description
Summary
Revision History
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