Altera HSMC Reference Manual page 30

A–6
Development Board
Table A–2. HSMC Port B Interface Pin-Out Information (Part 2 of 4)
Data Conversion HSMC Schematic
Board
Reference
(J1) Description
71 LVDS TX 4p or CMOS I/O data bit 20
72 LVDS RX 4p or CMOS I/O data bit 21
73 LVDS TX 4n or CMOS I/O data bit 22
74 LVDS RX 4n or CMOS I/O data bit 23
77 LVDS TX 5p or CMOS I/O data bit 24
78 LVDS RX 5p or CMOS I/O data bit 25
79 LVDS TX 5n or CMOS I/O data bit 26
80 LVDS RX 5n or CMOS I/O data bit 27
83 LVDS TX 6p or CMOS I/O data bit 28
84 LVDS RX 6p or CMOS I/O data bit 29
85 LVDS TX 6n or CMOS I/O data bit 30
86 LVDS RX 6n or CMOS I/O data bit 31
89 LVDS TX 7p or CMOS I/O data bit 32
90 LVDS RX 7p or CMOS I/O data bit 33
91 LVDS TX 7n or CMOS I/O data bit 34
92 LVDS RX 7n or CMOS I/O data bit 35
95 LVDS or CMOS clock out
96 LVDS or CMOS clock in
97 LVDS or CMOS clock out
98 LVDS or CMOS clock in
Data Conversion HSMC Reference Manual
Appendix A: Pin-Out Information for the Cyclone III (3C120)
Schematic Schematic
Signal Name Signal Name
ADA_D3 HSMB_TX_D_P4
ADB_D3 HSMB_RX_D_P4
ADA_D2 HSMB_TX_D_N4
ADB_D2 HSMB_RX_D_N4
ADA_D1 HSMB_TX_D_P5
ADB_D1 HSMB_RX_D_P5
ADA_D0 HSMB_TX_D_N5
ADB_D0 HSMB_RX_D_N5
ADA_OR HSMB_TX_D_P6
ADB_OR HSMB_RX_D_P6
ADA_OE HSMB_TX_D_N6
ADB_OE HSMB_RX_D_N6
ADA_SPI_CS HSMB_TX_D_P7
ADB_SPI_CS HSMB_RX_D_P7
AD_SDIO HSMB_TX_D_N7
AD_SCLK HSMB_RX_D_N7
FPGA_CLK_A_P HSMB_CLK_OUT_P1
XT_IN_P HSMB_CLK_IN_P1
FPGA_CLK_A_N HSMB_CLK_OUT_N1
XT_IN_N HSMB_CLK_IN_N1
Development Board Schematic
I/O
Standard
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
© November 2008 Altera Corporation
Cyclone
III
Pin
Number
R27
L27
R28
L28
R25
M27
R26
M28
U25
P25
U26
P26
V27
P27
V28
P28
AC26
J27
AD26
J28