D/A Converter Output Sma Connector (J12, J14); Audio Codec Converter (U5) - Altera HSMC Reference Manual

2–14
Table 2–15
Table 2–15. Differential to LVDS Clock Multiplexer (U11, U12) Pin-Out Information
Schematic Signal
FPGA_CLK_A_P
FPGA_CLK_A_N
FPGA_CLK_B_P
FPGA_CLK_B_N
XT_IN_P
XT_IN_N
DA(A,B)_CLK_SEL_P
DA(A,B)_CLK_SEL_N

D/A Converter Output SMA Connector (J12, J14)

J12 (channel A) and J14 (channel B) are standard through-hole SMA connectors used
to interface the DAC5672 D/A converter output with SMA cables.

Audio CODEC Converter (U5)

The Data Conversion HSMC contains three stereo jack and one mic jack connectors
which provide one stereo output, one stereo input, one amplified stereo headphone
output, and one microphone input. The stereo jacks are driven by a stereo audio
CODEC running at 8 to 96 kHz.
and manufacturing information.
Table 2–16. Audio CODEC Converter Component Reference
Board Reference
U5 Stereo Audio CODEC, 8–96 KHz, with
Integrated Headphone Amplifier
Table 2–17
Table 2–17. Audio CODEC Converter (U5) Pin-Out Information (Part 1 of 2)
HSMC Signal HSMC Pin
150
AIC_XCLK
146
AIC_LRCOUT
145
AIC_LRCIN
Data Conversion HSMC Reference Manual
provides the differential to LVDS clock multiplexer pin-out details.
HSMC
Connector
Pin Number Device Signal
95
PCLK0P
97
PCLK0N
155
PCLK1P
157
PCLK1N
96
PCLK2P
98
PCLK2N
—
QP
—
QN
Description
provides the TI TLV320AIC23 audio CODEC pin-out details.
Device
Device Signal Pin Number
25
XTI/MCLK
7
LRCOUT
5
LRCIN
Chapter 2: Board Components and Interfaces
Device
Pin Number
1 Non-inverting Differential clock input
2 Inverting Differential clock input
3 Non-inverting Differential clock input
4 Inverting Differential clock input
9 Non-inverting Differential clock input
10 Inverting Differential clock input
15 Non-inverting Differential Clock Output
14 Inverting Differential Clock Output
Table 2–16 lists the audio CODEC board reference
Manufacturing
Manufacturer Part Number
Texas Instruments TLV320AIC23
Description
Crystal or external-clock input. Used for derivation of all
internal clocks on the AIC23B.
I2S A/D converter-word clock signal. In audio master
mode, the AIC23B generates this framing signal and sends
it to the DSP. In audio slave mode, the signal is generated
by the DSP.
I2S D/A converter-word clock signal. In audio master
mode, the AIC23B generates this framing signal and sends
it to the DSP. In audio slave mode, the signal is generated
by the DSP.
Component Interfaces
Description
Manufacturer
Website
www.ti.com
© November 2008 Altera Corporation