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Chapter 2: Board Components and Interfaces
Component Interfaces
Table 2–11. A/D Converter Channel B (U2) Pin-Out Information (Part 2 of 2)
HSMC Signal
HSMC Pin
68
ADB_D4
66
ADB_D5
62
ADB_D6
60
ADB_D7
56
ADB_D8
54
ADB_D9
50
ADB_D10
48
ADB_D11
44
ADB_D12
42
ADB_D13
84
ADB_OR
91
AD_SDIO
92
AD_SCLK
90
ADB_SPI_CS
86
ADB_OE
158
ADB_DCO
—
—
—
Notes to
Table
2–11:
(1) This pin is connected to Multiplexer pin U10.15.
(2) This pin is connected to Multiplexer pin U10.14.
(3) This pin is connected to Jumper pin J6.2.
A/D Converter Clocks
Figure 2–5
the AD9254 A/D converter (U1 for channel A, U2 for channel B). J3 (channel A) or J7
(channel B) selects the A/D clock from the FPGA clock A, the FPGA clock B, or the
external SMA clock (J26 and J30). The selected A/D clock passes through a differential
to LVDS clock multiplexer (U9 for channel A, U10 for channel B), which provides the
clock signal to the AD9254.
© November 2008 Altera Corporation
Device Signal
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
OR
SDIO/DCS
SCLK/DFS
CSB
OEB
DCO
—
ADB_CLK_P
—
ADB_CLK_N
—
ADB_PWDN
shows the components involved in selecting the clock signal to be sent to
Device
Pin Number
3
Data Output Bit 4
4
Data Output Bit 5
5
Data Output Bit 6
6
Data Output Bit 7
9
Data Output Bit 8
10
Data Output Bit 9
11
Data Output Bit 10
12
Data Output Bit 11
13
Data Output Bit 12
14
Data Output Bit 13
15
Out-of-Range Indicator
18
Serial Port Interface (SPI) Data
Input/Output (Serial Port Mode)
19
Serial Port Interface Clock (Serial Port
Mode)
20
Serial Port Interface Chip Select
(Active Low)
43
Output Enable (Active Low)
44
Data Clock Output
38
(1)
Clock Input
39
(2)
Clock Input
36
(3)
Power-Down Function Select
Data Conversion HSMC Reference Manual
2–9
Description
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