Altera HSMC Reference Manual page 27

Appendix A: Pin-Out Information for the Cyclone III (3C120) Development Board
Table A–1. HSMC Port A Interface Pin-Out Information (Part 3 of 4)
Data Conversion HSMC Schematic
Board
Reference
(J1) Description
96 LVDS or CMOS clock in
97 LVDS or CMOS clock out
98 LVDS or CMOS clock in
101 LVDS TX 8p or CMOS I/O data bit 40
102 LVDS RX 8p or CMOS I/O data bit 41
103 LVDS TX 8n or CMOS I/O data bit 42
104 LVDS RX 8n or CMOS I/O data bit 43
107 LVDS TX 9p or CMOS I/O data bit 44
108 LVDS RX 9p or CMOS I/O data bit 45
109 LVDS TX 9n or CMOS I/O data bit 46
110 LVDS RX 9n or CMOS I/O data bit 47
113 LVDS TX 10p or CMOS I/O data bit 48
114 LVDS RX 10p or CMOS I/O data bit 49
115 LVDS TX 10n or CMOS I/O data bit 50
116 LVDS RX 10n or CMOS I/O data bit 51
119 LVDS TX 11p or CMOS I/O data bit 52
120 LVDS RX 11p or CMOS I/O data bit 53
121 LVDS TX 11n or CMOS I/O data bit 54
122 LVDS RX 11n or CMOS I/O data bit 55
125 LVDS TX 12p or CMOS I/O data bit 56
© November 2008 Altera Corporation
Schematic Schematic
Signal Name Signal Name
XT_IN_P HSMA_CLK_IN_P1
FPGA_CLK_A_N HSMA_CLK_OUT_N1
XT_IN_N HSMA_CLK_IN_N1
DA13 HSMA_TX_D_P8
DB13 HSMA_RX_D_P8
DA12 HSMA_TX_D_N8
DB12 HSMA_RX_D_N8
DA11 HSMA_TX_D_P9
DB11 HSMA_RX_D_P9
DA10 HSMA_TX_D_N9
DB10 HSMA_RX_D_N9
DA9 HSMA_TX_D_P10
DB9 HSMA_RX_D_P10
DA8 HSMA_TX_D_N10
DB8 HSMA_RX_D_N10
DA7 HSMA_TX_D_P11
DB7 HSMA_RX_D_P11
DA6 HSMA_TX_D_N11
DB6 HSMA_RX_D_N11
DA5 HSMA_TX_D_P12
Development Board Schematic
I/O
Standard
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
Data Conversion HSMC Reference Manual
A–3
Cyclone
III
Pin
Number
Y2
G5
Y1
L7
N4
L6
N3
K8
L4
L8
L3
K4
L2
K3
L1
J4
K2
J3
K1
J7