Altera HSMC Reference Manual page 34

B–2
Development Board
Table B–1. HSMC Port A Interface Pin-Out Information (Part 2 of 3)
Data Conversion HSMC Schematic
Board
Reference
(J1) Description
83 LVDS TX or CMOS I/O bit 6
84 LVDS RX or CMOS I/O bit 6
85 LVDS TX or CMOS I/O bit 6
86 LVDS RX or CMOS I/O bit 6
89 LVDS TX or CMOS I/O bit 7
90 LVDS RX or CMOS I/O bit 7
91 LVDS TX or CMOS I/O bit 7
92 LVDS RX or CMOS I/O bit 7
95 LVDS or CMOS clock out
96 LVDS or CMOS clock in
97 LVDS or CMOS clock out
98 LVDS or CMOS clock in
101 LVDS TX or CMOS I/O bit 8
102 LVDS RX or CMOS I/O bit 8
103 LVDS TX or CMOS I/O bit 8
104 LVDS RX or CMOS I/O bit 8
107 LVDS TX or CMOS I/O bit 9
108 LVDS RX or CMOS I/O bit 9
109 LVDS TX or CMOS I/O bit 9
110 LVDS RX or CMOS I/O bit 9
113 LVDS TX or CMOS I/O bit 10
114 LVDS RX or CMOS I/O bit 10 DB9
115 LVDS TX or CMOS I/O bit 10
116 LVDS RX or CMOS I/O bit 10 DB8
119 LVDS TX or CMOS I/O bit 11
120 LVDS RX or CMOS I/O bit 11 DB7
121 LVDS TX or CMOS I/O bit 11
122 LVDS RX or CMOS I/O bit 11 DB6
125 LVDS TX or CMOS I/O bit 12
126 LVDS RX or CMOS I/O bit 12 DB5
127 LVDS TX or CMOS I/O bit 12
128 LVDS RX or CMOS I/O bit 12 DB4
131 LVDS TX or CMOS I/O bit 13
132 LVDS RX or CMOS I/O bit 13 DB3
133 LVDS TX or CMOS I/O bit 13
134 LVDS RX or CMOS I/O bit 13 DB2
137 LVDS TX or CMOS I/O bit 14
Data Conversion HSMC Reference Manual
Appendix B: Pin-Out Information for the Stratix III (3SL150)
Schematic
Signal Name
ADA_OR HSMA_TX_P6
ADB_OR HSMA_RX_P6
ADA_OE HSMA_TX_N6
ADB_OE HSMA_RX_N6
ADA_SPI_CS HSMA_TX_P7
ADB_SPI_CS HSMA_RX_P7
AD_SDIO HSMA_TX_N7
AD_SCLK HSMA_RX_N7
FPGA_CLK_A_P HSMA_CLK_OUT_P1
XT_IN_P HSMA_CLK_IN_P1
FPGA_CLK_A_N HSMA_CLK_OUT_N1
XT_IN_N HSMA_CLK_IN_N1
DA13 HSMA_TX_P8
DB13 HSMA_RX_P8
DA12 HSMA_TX_N8
DB12 HSMA_RX_N8
DA11 HSMA_TX_P9
DB11 HSMA_RX_P9
DA10 HSMA_TX_N9
DB10 HSMA_RX_N9
DA9 HSMA_TX_P10
HSMA_RX_P10
DA8 HSMA_TX_N10
HSMA_RX_N10
DA7 HSMA_TX_P11
HSMA_RX_P11
DA6 HSMA_TX_N11
HSMA_RX_N11
DA5 HSMA_TX_P12
HSMA_RX_P12
DA4 HSMA_TX_N12
HSMA_RX_N12
DA3 HSMA_TX_P13
HSMA_RX_P13
DA2 HSMA_TX_N13
HSMA_RX_N13
DA1 HSMA_TX_P14
Development Board Schematic
Schematic
Signal Name I/O Standard
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
© November 2008 Altera Corporation
Stratix III
Pin
Number
AE6
AF4
AE5
AF3
AD4
AG1
AD3
AH1
V10
Y4
W9
W3
AC6
AF2
AC5
AF1
AB6
AE2
AB5
AE1
AB8
AE4
AC7
AE3
Y6
AC2
Y5
AD1
AA7
AB2
AA6
AC1
Y8
AA1
Y7
AB1
Y10