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2–10
Figure 2–5. A/D Converter Clocking Options
ADA_OE
ADA_CLK_P
ADA_CLK_N
ADA_SPI_CS
ADA_SDIO
ADA_ACLK
FPGA_CLK_A_P
FPGA_CLK_A_N
FPGA_CLK_B_P
FPGA_CLK_B_N
XT_IN_P
XT_IN_N
NO_CLK_P
NO_CLK_N
ADB_OE
ADB_CLK_P
ADB_CLK_N
ADB_SPI_CS
AD_SDIO
AD_SCLK
FPGA_CLK_A_P
FPGA_CLK_A_N
FPGA_CLK_B_P
FPGA_CLK_B_N
XT_IN_P
XT_IN_N
NO_CLK_P
NO_CLK_N
Table 2–12
Table 2–12. Differential to LVDS Clock Multiplexer (U9, U10) Pin-Out Information (Part 1 of 2)
Schematic Signal
FPGA_CLK_A_P
FPGA_CLK_A_N
FPGA_CLK_B_P
FPGA_CLK_B_N
Data Conversion HSMC Reference Manual
ADA_OE
ADA_CLK_P
ADA_CLK_N
ADA_SPI_CS
ADA_SDIO
ADA_SCLK
U9
FPGA_CLK_A_P
1
PCLK0P
FPGA_CLK_A_N
2
PCLK0N
FPGA_CLK_B_P
3
PCLK1P
FPGA_CLK_B_N
4
PCLK1N
XT_IN_P
9
PCLK2P
XT_IN_N
10
PCLK2N
NO_CLK_P
11
PCLK3P
12
NO_CLK_N
PCLK3N
ADA_CLK_S0
6
SEL0
ADA_CLK_S1
7
SEL1
ADB_OE
ADB_CLK_P
ADB_CLK_N
ADB_SPI_CS
AD_SDIO
AD_SCLK
U10
FPGA_CLK_A_P
1
PCLK0P
FPGA_CLK_A_N
2
PCLK0N
FPGA_CLK_B_P
3
PCLK1P
FPGA_CLK_B_N
4
PCLK1N
XT_IN_P
9
PCLK2P
XT_IN_N
10
PCLK2N
NO_CLK_P
11
PCLK3P
12
NO_CLK_N
PCLK3N
ADB_CLK_S0
6
SEL0
ADB_CLK_S1
7
SEL1
provides the differential to LVDS clock multiplexer pin-out details.
HSMC
Connector
Pin Number
Device Signal
95
PCLK0P
97
PCLK0N
155
PCLK1P
157
PCLK1N
Chapter 2: Board Components and Interfaces
5
VDD
16
VDD
ADA_CLK_SEL_P
15
QP
14
ADA_CLK_SEL_N
QN
13
GND
8
GND
ICS854054
5
VDD
16
VDD
ADB_CLK_SEL_P
15
QP
14
ADB_CLK_SEL_N
QN
13
GND
8
GND
ICS854054
Device Pin
Number
1
Non-inverting Differential clock input
2
Inverting Differential clock input
3
Non-inverting Differential clock input
4
Inverting Differential clock input
Component Interfaces
3.3 V
C98
C99
C100
10µF 0.1µF 1.0nF
3.3 V
C101 C102
0.1µF
1.0nF
Description
© November 2008 Altera Corporation
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