Altera HSMC Reference Manual page 36

B–4
Development Board
Table B–2. HSMC Port B Interface Pin-Out Information (Part 2 of 3)
Data Conversion HSMC Schematic
Board
Reference
(J1) Description
60 LVDS RX or CMOS I/O bit 2
61 LVDS TX or CMOS I/O bit 2
62 LVDS RX or CMOS I/O bit 2
65 LVDS TX or CMOS I/O bit 3
66 LVDS RX or CMOS I/O bit 3
67 LVDS TX or CMOS I/O bit 3
68 LVDS RX or CMOS I/O bit 3
71 LVDS TX or CMOS I/O bit 4
72 LVDS RX or CMOS I/O bit 4
73 LVDS TX or CMOS I/O bit 4
74 LVDS RX or CMOS I/O bit 4
77 LVDS TX or CMOS I/O bit 5
78 LVDS RX or CMOS I/O bit 5
79 LVDS TX or CMOS I/O bit 5
80 LVDS RX or CMOS I/O bit 5
83 LVDS TX or CMOS I/O bit 6
84 LVDS RX or CMOS I/O bit 6
85 LVDS TX or CMOS I/O bit 6
86 LVDS RX or CMOS I/O bit 6
89 LVDS TX or CMOS I/O bit 7
90 LVDS RX or CMOS I/O bit 7
91 LVDS TX or CMOS I/O bit 7
92 LVDS RX or CMOS I/O bit 7
95 LVDS or CMOS clock out
96 LVDS or CMOS clock in
97 LVDS or CMOS clock out
98 LVDS or CMOS clock in
101 LVDS TX or CMOS I/O bit 8
102 LVDS RX or CMOS I/O bit 8
103 LVDS TX or CMOS I/O bit 8
104 LVDS RX or CMOS I/O bit 8
107 LVDS TX or CMOS I/O bit 9
108 LVDS TX or CMOS I/O bit 9
109 LVDS RX or CMOS I/O bit 9
110 LVDS RX or CMOS I/O bit 9
113 LVDS TX or CMOS I/O bit 10
114 LVDS RX or CMOS I/O bit 10 DB9
Data Conversion HSMC Reference Manual
Appendix B: Pin-Out Information for the Stratix III (3SL150)
Schematic
Signal Name
ADB_D7 HSMB_RX_P2
ADA_D6 HSMB_TX_N2
ADB_D6 HSMB_RX_N2
ADA_D5 HSMB_TX_P3
ADB_D5 HSMB_RX_P3
ADA_D4 HSMB_TX_N3
ADB_D4 HSMB_RX_N3
ADA_D3 HSMB_TX_P4
ADB_D3 HSMB_RX_P4
ADA_D2 HSMB_TX_N4
ADB_D2 HSMB_RX_N4
ADA_D1 HSMB_TX_P5
ADB_D1 HSMB_RX_P5
ADA_D0 HSMB_TX_N5
ADB_D0 HSMB_RX_N5
ADA_OR HSMB_TX_P6
ADB_OR HSMB_RX_P6
ADA_OE HSMB_TX_N6
ADB_OE HSMB_RX_N6
ADA_SPI_CS HSMB_TX_P7
ADB_SPI_CS HSMB_RX_P7
AD_SDIO HSMB_TX_N7
AD_SCLK HSMB_RX_N7
FPGA_CLK_A_P HSMB_CLK_OUT_P1
XT_IN_P HSMB_CLK_IN_P1
FPGA_CLK_A_N HSMB_CLK_OUT_N1
XT_IN_N HSMB_CLK_IN_N1
DA13 HSMB_TX_P8
DB13 HSMB_RX_P8
DA12 HSMB_TX_N8
DB12 HSMB_RX_N8
DA11 HSMB_TX_P9
DB11 HSMB_RX_P9
DA10 HSMB_TX_N9
DB10 HSMB_RX_N9
DA9 HSMB_TX_P10
HSMB_RX_P10
Development Board Schematic
Schematic
Signal Name I/O Standard
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
LVDS or 2.5 V
© November 2008 Altera Corporation
Stratix III
Pin
Number
P2
U6
R1
T5
N2
T4
P1
R10
M1
R9
N1
R7
L2
R6
L1
N9
K4
N8
K3
M7
J4
M6
J3
P6
N4
P5
N3
L7
H2
L6
J1
L5
G2
L4
H1
K6
F1