Altera HSMC Reference Manual page 25

Table A–1
EP3C120F780 development board.
Table A–1. HSMC Port A Interface Pin-Out Information (Part 1 of 4)
Data Conversion HSMC Schematic
Board
Reference
(J1) Description
33 Management serial data
34 Management serial clock
41 Dedicated CMOS I/O bit 0
42 Dedicated CMOS I/O bit 1
43 Dedicated CMOS I/O bit 2
44 Dedicated CMOS I/O bit 3
47 LVDS TX or CMOS I/O bit 0
48 LVDS RX or CMOS I/O bit 0
49 LVDS TX or CMOS I/O bit 0
50 LVDS RX or CMOS I/O bit 0
53 LVDS TX bit 1p or CMOS I/O data 8
54 LVDS RX bit 1p or CMOS I/O data 9
55 LVDS TX bit 1n or CMOS I/O data bit 10 ADA_D8
56 LVDS RX bit 1n or CMOS I/O data bit 11 ADB_D8
59 LVDS TX bit 2p or CMOS I/O data bit 12 ADA_D7
60 LVDS RX bit 2p or CMOS I/O data bit 13 ADB_D7
61 LVDS TX bit 2n or CMOS I/O data bit 14 ADA_D6
62 LVDS RX bit 2n or CMOS I/O data bit 15 ADB_D6
65 LVDS TX bit 3p or CMOS I/O data bit 16 ADA_D5
© November 2008 Altera Corporation
A. Pin-Out Information for the Cyclone III
provides the HSMC Port A interface pin-out information for the Cyclone III
Schematic
Signal Name
SDA
SCL
ADA_D13
ADB_D13
ADA_D12
ADB_D12
ADA_D11
ADB_D11
ADA_D10
ADB_D10
ADA_D9
ADB_D9
(3C120) Development Board
Development Board Schematic
Schematic
Signal Name
HSMA_SDA
HSMA_SCL
HSMA_D0
HSMA_D1
HSMA_D2
HSMA_D3
HSMA_TX_D_P0
HSMA_RX_D_P0
HSMA_TX_D_N0
HSMA_RX_D_N0
HSMA_TX_D_P1
HSMA_RX_D_P1
HSMA_TX_D_N1
HSMA_RX_D_N1
HSMA_TX_D_P2
HSMA_RX_D_P2
HSMA_TX_D_N2
HSMA_RX_D_N2
HSMA_TX_D_P3
Data Conversion HSMC Reference Manual
Cyclone
III
I/O Pin
Standard Number
2.5 V AC1
2.5 V AC3
2.5 V AB6
2.5 V AF2
2.5 V AE3
2.5 V AC5
LVDS or R7
2.5 V
LVDS or AB2
2.5 V
LVDS or R6
2.5 V
LVDS or AB1
2.5 V
LVDS or V4
2.5 V
LVDS or Y4
2.5 V
LVDS or V3
2.5 V
LVDS or Y3
2.5 V
LVDS or T4
2.5 V
LVDS or U3
2.5 V
LVDS or T3
2.5 V
LVDS or U4
2.5 V
LVDS or R3
2.5 V