Altera HSMC Reference Manual page 32

A–8
Development Board
Table A–2. HSMC Port B Interface Pin-Out Information (Part 4 of 4)
Data Conversion HSMC Schematic
Board
Reference
(J1) Description
131 LVDS TX 13p or CMOS I/O data bit 60
132 LVDS RX 13p or CMOS I/O data bit 61
133 LVDS TX 13n or CMOS I/O data bit 62
134 LVDS RX 13n or CMOS I/O data bit 63
137 LVDS TX 14p or CMOS I/O data bit 64
138 LVDS TX 14p or CMOS I/O data bit 65
139 LVDS RX 14n or CMOS I/O data bit 66
140 LVDS RX 14n or CMOS I/O data bit 67
143 LVDS RX 15p or CMOS I/O data bit 68
144 LVDS TX 15p or CMOS I/O data bit 69
145 LVDS RX 15n or CMOS I/O data bit 70
146 LVDS RX 15n or CMOS I/O data bit 70
149 LVDS RX 16p or CMOS I/O data bit 72
150 LVDS TX 16p or CMOS I/O data bit 73
151 LVDS TX 16n or CMOS I/O data bit 74
155 LVDS or CMOS clock out
156 LVDS or CMOS clock in
157 LVDS or CMOS clock out
158 LVDS or CMOS clock in
Data Conversion HSMC Reference Manual
Appendix A: Pin-Out Information for the Cyclone III (3C120)
Schematic Schematic
Signal Name Signal Name
DA3 HSMB_TX_D_P13
DB3 HSMB_RX_D_P13
DA2 HSMB_TX_D_N13
DB2 HSMB_RX_D_N13
DA1 HSMB_TX_D_P14
DB1 HSMB_RX_D_P14
DA0 HSMB_TX_D_N14
DB0 HSMB_RX_D_N14
AIC_DIN HSMB_TX_D_P15
AIC_DOUT HSMB_RX_D_P15
AIC_LRCIN HSMB_TX_D_N15
AIC_LRCOUT HSMB_RX_D_N15
AIC_BCLK HSMB_TX_D_P16
AIC_XCLK HSMB_RX_D_P16
AIC_SPI_CS HSMB_TX_D_N16
FPGA_CLK_B_P HSMB_CLK_OUT_P2
ADA_DCO HSMB_CLK_IN_P2
FPGA_CLK_B_N HSMB_CLK_OUT_N2
ADB_DCO HSMB_CLK_IN_N2
Development Board Schematic
I/O
Standard
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS or
2.5 V
LVDS
LVDS
2.5 V
2.5 V
© November 2008 Altera Corporation
Cyclone
III
Pin
Number
Y23
W28
Y24
W27
AE27
V23
AE28
V24
W22
AB27
Y22
AB28
V21
AC27
W21
AD27
Y27
AD28
Y28