D/A Converter Clocks - Altera HSMC Reference Manual

Chapter 2: Board Components and Interfaces
Component Interfaces

D/A Converter Clocks

Figure 2–6
the DAC5672 (U3 for channels A and B). J15 (channel A) or J17 (channel B) selects the
D/A clock from the FPGA clock A, the FPGA clock B, or the SMA clock (J26 and J30).
The selected D/A clock passes through a differential to LVDS clock multiplexer (U11
for channel A, U12 for channel B), which provides the clock signal to 2-bit high-speed
differential receiver FIN1028, which in turn outputs clock to the DAC5672 (refer to
"D/A Converter Clock Select Jumper (J15, J17)" on page
Figure 2–6. D/A Converter Clocking Options
FPGA_CLK_A_P
FPGA_CLK_A_N
FPGA_CLK_B_P
FPGA_CLK_B_N
XT_IN_P
XT_IN_N
NO_CLK_P
NO_CLK_N
FPGA_CLK_A_P
FPGA_CLK_A_N
FPGA_CLK_B_P
FPGA_CLK_B_N
XT_IN_P
XT_IN_N
NO_CLK_P
NO_CLK_N
© November 2008 Altera Corporation
shows the components involved in selecting the clock signal to be sent to
U11
FPGA_CLK_A_P
1
PCLK0P
FPGA_CLK_A_N 2
PCLK0N
FPGA_CLK_B_P
3
PCLK1P
FPGA_CLK_B_N
4
PCLK1N
XT_IN_P
9
PCLK2P
XT_IN_N
10
PCLK2N
NO_CLK_P 11
PCLK3P
12
NO_CLK_N
PCLK3N
DAA_CLK_S0
6
SEL0
7
DAA_CLK_S1
SEL1
ICS854054
U12
FPGA_CLK_A_P
1
PCLK0P
FPGA_CLK_A_N 2
PCLK0N
FPGA_CLK_B_P
3
PCLK1P
FPGA_CLK_B_N
4
PCLK1N
XT_IN_P
9
PCLK2P
XT_IN_N 10
PCLK2N
NO_CLK_P 11
PCLK3P
12
NO_CLK_N
PCLK3N
DAB_CLK_S0
6
SEL0
7
DAB_CLK_S1
SEL1
ICS854054
2–4.)
3.3 V
C103 C104
0.1µF 1.0nF
5
VDD
16
VDD
DAC_CLK_1_P
15
QP
14 DAC_CLK_1_N
QN
13
GND
8
GND
3.3 V
C105 C106
0.1µF 1.0nF
5
VDD
16
VDD
DAC_CLK_2_P
15
QP
14
DAC_CLK_2_N
QN
13
GND
8
GND
Data Conversion HSMC Reference Manual
2–13