Xadc Power System Measurement - Xilinx AC701 User Manual

The LMZ31503 and LMZ31700 family adjustable voltage regulators have their output
voltage set by an external resistor. The regulator topology on the AC701 board permits the
UCD90120A to monitor rail voltage and current. Voltage margining at +5% and -5% is also
implemented.
Each voltage regulator external V
the regulator is standalone. The UCD90120A has two ADC inputs allocated per voltage
rail, one input for the remote voltage sense connection, the other for the current sense
resistor op amp output voltage connection. The UCD90120A ADC full scale input is 2.5V.
The remote voltage feedback is scaled to approximately 2V if it exceeds 2V—that is, the
VCCO_VADJ rail for the 2.5V and 3.3V modes, and the FPGA_3V3 rail also at 3.3V are
resistor attenuated to scale the remotely sensed voltage at 0.606 to give approximately 2V
at the ADC input pin for a 3.3V remote sense value. Rails below 2V are not scaled.
Each rail current sense op amp has its gain set to provide approximately 2V maximum at
the TI UCD90120A ADC input pin when the rail current is at its expected maximum
current level, as shown in
The UCD90120A has an assignable group of GPIO pins with PWM capability. Each
controller channel has a PWM GPIO pin connected to the associated voltage regulator
V
is configured in 3-state mode. This pin is not driven unless a Margin command is executed.
The Margin command is available within the TI Fusion Digital Power Designer software.
During the margin high or low operation, the PWM GPIO pin drives a voltage into the
voltage regulator V
V

XADC Power System Measurement

The AC701 board XADC interface includes power system voltage and current measuring
capability. The V
XADC internal voltage measurement capability. Other rails are measured through two
external Analog Devices ADG707BRU multiplexers U14 and U13. Each rail has a TI
INA333 op amp strapped across its series current sense resistor Kelvin terminals. This op
amp has its gain adjusted to give approximately 1V at the expected full scale current value
for the rail.
AC701 Evaluation Board
UG952 (v1.3) April 7, 2015
Figure 1-44
pin. The external V
ADJ OUT
pin, which causes a slight voltage change resulting in the regulator
ADJ
moving to the margin +5% or -5% voltage commanded.
OUT
, V
CCINT CCAUX
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setting resistor is calculated and implemented as if
OUT
(U8 controller #1) and
setting resistor is also wired to this pin. The PWM GPIO pin
and V rail voltages are measured through the
CCBRAM
Feature Descriptions
Figure 1-45 (U9 controller #2).
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