Digital Equipment DIGITAL Server 7100 1200 Service Maintenance Manual page 44

Menu Fields
2nd OPB CPU
Line Read Pre-
Fetch
CPU in order
queue depth
APIC & MP table
ECC interrupt
GAT mode
System arbitration
(1)
Factory default setting
Settings
Disabled
(1)
Enabled
(1)
8
1
Disabled
MPS 1.1
(1)
MPS 1.4
(1)
Disabled
IRQ14, Shared
IRQ14, Non-Shared
IRQ15, Shared
IRQ15, Non-Shared
(1)
Enabled
Disabled
(1)
CPU Bus first
EISA Bus first
Full Rotation
Comments
When enabled, allows the 2nd OPB's PCI memory
read line commands to pre-fetch additional processor
cache lines.
Allows you to select the depth of the processor in-
order-queue.
Applicable to single processor configurations only,
always enabled for Multi-Processing (MP) operating
system configurations. When set to MPS 1.1 or MPS
1.4, the processor's Advanced Programmable
Interrupt Controller (APIC) is enabled, and the MP
table used by MP operating systems will be created.
Note: This parameter must be disabled for NetWare
3.12 single processor systems.
Enables the Error Correction Code (ECC) interrupt. If
enabled, you can select IRQ14 or IRQ15 as the ECC
interrupt. You can also define the IRQ as shared with
other devices, such as EISA or PCI devices.
Should be enabled only when an ISA bus mastering
card is installed in the server. Disable it for all other
configurations.
This option controls the operating modes of the
server's PCI arbiter. The arbiter controls the
arbitration priorities for EISA, PCI, and processor
buses.
SCU Features
3-11