Panasonic FP0H User Manual page 149

 Allocation of control codes
• The following bits are allocated according to the specified channel and functions.
FP0H mode
bit no. 15
Channel specification
H0 to H3: CH0 to CH3
H00: Fixed
High-speed counter
0: Continue 1: Cancel
instruction
External reset input 0: Valid 1: Invalid
Count 0: Enable 1: Disable
Software reset 0: Disable 1: Enable
• When controlling the above functions using external inputs, arbitrary inputs can be allocated.
 Example of program
The following example shows the program for performing the software reset of the high-speed
counter CH0 using the input X7.
X7
DF
（ ）
REFERENCE
• For details of the allocations of I/O and flags, refer to "12.2.4 When Using
High-speed Counter Function".
• For details of the FPΣ mode, refer to "11. FPΣ Mode".
8 7 0
0 0 0 0 0 0 0 0
H1 DT90052
F0 MV
H0 DT90052
F0 MV
10.3 High-speed Counter Instruction
FPΣ mode
bit no. 15
Channel specification
H0 to H3: CH0 to CH3
Near home input 0: Invalid, 1:Valid
High-speed counter instruction clear
pulse output stop 0: Continue, 1: Clear, stop
Reset input setting 0: Valid, 1: Invalid
Count 0: Enable 1: Disable
Software reset 0: Disable, 1: Enable
4 3 2 1 0
10-9