Alternate Functions Of Port D - Atmel ATmega128 Manual

Alternate Functions of
Port D
ATmega128
78
Table 35. Overriding Signals for Alternate Functions in PC3..PC0
Signal
Name PC3/A11
PUOE SRE • (XMM<5)
PUOV 0
DDOE SRE • (XMM<5)
DDOV 1
PVOE SRE • (XMM<5)
PVOV A11
DIEOE 0
DIEOV 0
DI –
AIO –
Note: 1. XMM = 0 in ATmega103 compatibility mode.
The Port D pins with alternate functions are shown in
Table 36. Port D Pins Alternate Functions
Port Pin Alternate Function
PD7 T2 (Timer/Counter2 Clock Input)
PD6 T1 (Timer/Counter1 Clock Input)
(1)
PD5 XCK1 (USART1 External Clock Input/Output)
PD4 ICP1 (Timer/Counter1 Input Capture Pin)
PD3 INT3/TXD1
PD2 INT2/RXD1
(1)
PD1 INT1/SDA
(1)
PD0 INT0/SCL
Note: 1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode.
The alternate pin configuration is as follows:
• T2 – Port D, Bit 7
T2, Timer/Counter2 counter source.
• T1 – Port D, Bit 6
T1, Timer/Counter1 counter source.
• XCK1 – Port D, Bit 5
XCK1, USART1 External clock. The Data Direction Register (DDD4) controls whether the clock
is output (DDD4 set) or input (DDD4 cleared). The XCK1 pin is active only when the USART1
operates in Synchronous mode.
PC2/A10
SRE • (XMM<6)
0
SRE • (XMM<6)
1
SRE • (XMM<6)
A10
0
0
–
–
(1)
(External Interrupt3 Input or UART1 Transmit Pin)
(1)
(External Interrupt2 Input or UART1 Receive Pin)
(External Interrupt1 Input or TWI Serial DAta)
(External Interrupt0 Input or TWI Serial CLock)
(1)
PC1/A9 PC0/A8
SRE • (XMM<7) SRE • (XMM<7)
0 0
SRE • (XMM<7) SRE • (XMM<7)
1 1
SRE • (XMM<7) SRE • (XMM<7)
A9 A8
0 0
0 0
– –
– –
Table 36.
2467S–AVR–07/09