Atmel ATmega128 Manual page 146

8-bit
Timer/Counter2
with PWM
Overview
Registers
ATmega128
146
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main
features are:
•
Single Channel Counter
•
Clear Timer on Compare Match (Auto Reload)
•
Glitch-free, Phase Correct Pulse width Modulator (PWM)
•
Frequency Generator
•
External Event Counter
•
10-bit Clock Prescaler
•
Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)
A simplified block diagram of the 8-bit Timer/Counter is shown in
ment of I/O pins, refer to
I/O bits and I/O pins, are shown in bold. The device-specific I/O register and bit locations are
listed in the "8-bit Timer/Counter Register Description" on page
Figure 61. 8-Bit Timer/Counter Block Diagram
Timer/Counter
TCNTn
=
OCRn
The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt
request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag
Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other
timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T2 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the clock select logic is referred to as the timer clock (clk
"Pin Configurations" on page
TCCRn
count
clear
Control Logic
direction
BOTTOM TOP
= 0 =
0xFF
Figure 61. For the actual place-
2. CPU accessible I/O registers, including
157.
Clock Select
clk
Tn
Edge
Detector
( From Prescaler )
Waveform
Generation
TOVn
(Int.Req.)
Tn
OCn
(Int.Req.)
OCn
).
T2
2467S–AVR–07/09