Atmel ATmega128 Manual page 168

ATmega128
168
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to Figure 77
rized below:
Table 70. CPOL functionality
CPOL
0
1
• Bit 2 – CPHA: Clock Phase
The settings of the clock phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
tionality is summarized below:
Table 71. CPHA functionality
CPHA
0
1
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have
no effect on the slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 72. Relationship Between SCK and the Oscillator Frequency
SPI2X SPR1
0
0
0
0
1
1
1
1
and Figure 78 for an example. The CPOL functionality is summa-
Leading edge
Rising
Falling
Figure 77 and
Leading edge
Sample
Setup
SPR0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Trailing edge
Falling
Rising
Figure 78 for an example. The CPHA func-
Trailing edge
Setup
Sample
SCK Frequency
f /
4
osc
f /
16
osc
f /
64
osc
f /
128
osc
f /
2
osc
f /
8
osc
f /
32
osc
f /
64
osc
is
osc
2467S–AVR–07/09