Data Modes - Atmel ATmega128 Manual

Data Modes

ATmega128
170
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
77 and Figure 78. Data bits are shifted out and latched in on opposite edges of the SCK signal,
ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
70 and Table 71, as done below:
Table 73. CPOL and CPHA Functionality
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
Figure 77. SPI Transfer Format with CPHA = 0
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
Figure 78. SPI Transfer Format with CPHA = 1
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
Leading edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
MSB Bit 6 Bit 5 Bit 4
LSB Bit 1 Bit 2 Bit 3
MSB Bit 6 Bit 5
LSB Bit 1 Bit 2
Trailing edge SPI mode
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
Bit 3 Bit 2 Bit 1
Bit 4 Bit 5 Bit 6
Bit 4 Bit 3 Bit 2 Bit 1
Bit 3 Bit 4 Bit 5 Bit 6
Figure
Table
0
1
2
3
LSB
MSB
LSB
MSB
2467S–AVR–07/09