Page 1: Features
Features ® • High Performance, Low Power AVR 8-Bit Microcontroller • Advanced RISC Architecture – 131 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz –...
Page 2: Pin Configurations
ATmega48P/88P/168P/328P 1. Pin Configurations Figure 1-1. Pinout ATmega48P/88P/168P/328P TQFP Top View PDIP (PCINT14/RESET) PC6 PC5 (ADC5/SCL/PCINT13) (PCINT16/RXD) PD0 PC4 (ADC4/SDA/PCINT12) (PCINT17/TXD) PD1 PC3 (ADC3/PCINT11) (PCINT19/OC2B/INT1) PD3 PC1 (ADC1/PCINT9) (PCINT18/INT0) PD2 PC2 (ADC2/PCINT10) (PCINT20/XCK/T0) PD4 PC0 (ADC0/PCINT8) (PCINT19/OC2B/INT1) PD3 PC1 (ADC1/PCINT9) ADC7 (PCINT20/XCK/T0) PD4 PC0 (ADC0/PCINT8)
Page 3: Pin Descriptions
ATmega48P/88P/168P/328P Pin Descriptions 1.1.1 Digital supply voltage. 1.1.2 Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability.
Page 4: Overview
ATmega48P/88P/168P/328P The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page 1.1.7 is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally connected to V , even if the ADC is not used. If the ADC is used, it should be connected to V through a low-pass filter.
Page 5: Block Diagram
ATmega48P/88P/168P/328P Block Diagram Figure 2-1. Block Diagram Watchdog Power debugWIRE Timer Supervision POR / BOD & Watchdog PROGRAM RESET LOGIC Oscillator Oscillator Flash SRAM Circuits / Clock Generation EEPROM AVCC AREF 8bit T/C 0 16bit T/C 1 A/D Conv. Analog Internal 8bit T/C 2 Comp.
Page 6: Comparison Between Atmega48P, Atmega88P, Atmega168P, And Atmega328P
This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro- gram running on the AVR core.
Page 7: About
Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
Page 8: Avr Cpu Core
ATmega48P/88P/168P/328P 4. AVR CPU Core Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 4-1.
Page 9: Alu - Arithmetic Logic Unit
ATmega48P/88P/168P/328P ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –...
Page 10 ATmega48P/88P/168P/328P specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt.
Page 11: General Purpose Register File
ATmega48P/88P/168P/328P General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input •...
Page 12: Stack Pointer
ATmega48P/88P/168P/328P 4.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3.
Page 13: Instruction Execution Timing
ATmega48P/88P/168P/328P 4.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 0x3D (0x5D) Read/Write Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND...
Page 14: Reset And Interrupt Handling
ATmega48P/88P/168P/328P Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
Page 15 ATmega48P/88P/168P/328P Assembly Code Example in r16, SREG ; store SREG value ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG;...
Page 16: Avr Memories
ATmega48P/88P/168P/328P 5. AVR Memories Overview This section describes the different memories in the ATmega48P/88P/168P/328P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega48P/88P/168P/328P features an EEPROM Memory for data storage. All three memory spaces are linear and regular.
Page 17 ATmega48P/88P/168P/328P Figure 5-1. Program Memory Map, ATmega48P Program Memory 0x0000 Application Flash Section 0x7FF Figure 5-2. Program Memory Map, ATmega88P, ATmega168P, and ATmega328P Program Memory 0x0000 Application Flash Section Boot Flash Section 0x0FFF/0x1FFF/0x3FFF 8025I–AVR–02/09...
Page 18: Sram Data Memory
ATmega48P/88P/168P/328P SRAM Data Memory Figure 5-3 shows how the ATmega48P/88P/168P/328P SRAM Memory is organized. The ATmega48P/88P/168P/328P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instruc- tions.
Page 19: Eeprom Data Memory
ATmega48P/88P/168P/328P 5.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk cycles as described in Figure 5-4. Figure 5-4. On-chip Data SRAM Access Cycles Address Address valid Compute Address...
Page 20: I/O Memory
ATmega48P/88P/168P/328P 5.4.2 Preventing EEPROM Corruption During periods of low V the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low.
Page 21: Register Description
ATmega48P/88P/168P/328P Register Description 5.6.1 EEARH and EEARL – The EEPROM Address Register 0x22 (0x42) – – – – – – – EEAR8 EEARH 0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL Read/Write Initial Value • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega48P/88P/168P/328P and will always read as zero.
Page 22 ATmega48P/88P/168P/328P is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 5-1. EEPROM Mode Bits Programming EEPM1 EEPM0 Time Operation 3.4 ms Erase and Write in one operation (Atomic Operation) 1.8 ms Erase Only 1.8 ms...
Page 23 ATmega48P/88P/168P/328P When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. •...
Page 24 ATmega48P/88P/168P/328P Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ;...
Page 25 ATmega48P/88P/168P/328P The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ;...
Page 26: System Clock And Clock Options
ATmega48P/88P/168P/328P 6. System Clock and Clock Options Clock Systems and their Distribution Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power Manage- ment and Sleep Modes”...
Page 27: Clock Sources
ATmega48P/88P/168P/328P 6.1.4 Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 6.1.5 ADC Clock –...
Page 28: Low Power Crystal Oscillator
ATmega48P/88P/168P/328P selectable delays are shown in Table 6-2. The frequency of the Watchdog Oscillator is voltage dependent as shown in ”Typical Characteristics” on page 328. Table 6-2. Number of Watchdog Oscillator Cycles Typ Time-out (V = 5.0V) Typ Time-out (V = 3.0V) Number of Cycles 0 ms...
Page 29 ATmega48P/88P/168P/328P Figure 6-2. Crystal Oscillator Connections XTAL2 (TOSC2) XTAL1 (TOSC1) The Low Power Oscillator can operate in three different modes, each optimized for a specific fre- quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6-3 on page Table 6-3.
Page 30: Full Swing Crystal Oscillator
ATmega48P/88P/168P/328P Table 6-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection (Continued) Start-up Time from Additional Delay Oscillator Source / Power-down and from Reset Power Conditions Power-save = 5.0V) CKSEL0 SUT1..0 Crystal Oscillator, BOD 16K CK 14CK enabled Crystal Oscillator, fast 16K CK 14CK + 4.1 ms...
Page 31 ATmega48P/88P/168P/328P Figure 6-3. Crystal Oscillator Connections XTAL2 (TOSC2) XTAL1 (TOSC1) Table 6-6. Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Additional Delay Oscillator Source / Power-down and from Reset Power Conditions Power-save = 5.0V) CKSEL0 SUT1..0 Ceramic resonator, fast 258 CK...
Page 32: Low Frequency Crystal Oscillator
ATmega48P/88P/168P/328P Low Frequency Crystal Oscillator The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals, load capasitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega48P/88P/168P/328P oscillator is optimized for very low power consumption, and thus when selecting crystals, see Table 6-7 on page 32...
Page 33: Calibrated Internal Rc Oscillator
ATmega48P/88P/168P/328P Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 26-1 on page 319 for more details. The device is shipped with the CKDIV8 Fuse programmed. ”System Clock Prescaler”...
Page 34: External Clock
ATmega48P/88P/168P/328P Table 6-12. 128 kHz Internal Oscillator Operating Modes Nominal Frequency CKSEL3..0 128 kHz 0011 Note: 1. Note that the 128 kHz oscillator is a very low power clock source, and is not designed for a high accuracy. When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-13.
Page 35: Clock Output Buffer
ATmega48P/88P/168P/328P Table 6-15. Start-up Times for the External Clock Selection Start-up Time from Power- Additional Delay from Power Conditions down and Power-save Reset (V = 5.0V) SUT1..0 BOD enabled 6 CK 14CK Fast rising power 6 CK 14CK + 4.1 ms Slowly rising power 6 CK 14CK + 65 ms...
Page 36 ATmega48P/88P/168P/328P neither the clock frequency corresponding to the previous setting, nor the clock frequency corre- sponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted.
Page 37: Register Description
ATmega48P/88P/168P/328P 6.12 Register Description 6.12.1 OSCCAL – Oscillator Calibration Register (0x66) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL Read/Write Initial Value Device Specific Calibration Value • Bits 7..0 – CAL7..0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
Page 38 ATmega48P/88P/168P/328P The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions.
Page 39: Power Management And Sleep Modes
ATmega48P/88P/168P/328P 7. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods.
Page 40: Bod Disable
ATmega48P/88P/168P/328P BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 25-7 on page 297, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 7-1 on page 39.
Page 41: Power-Down Mode
ATmega48P/88P/168P/328P Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2- wire Serial Interface address watch, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, a 2-wire Serial Interface address match, an external level interrupt on INT0 or INT1, or a pin change interrupt can wake up the MCU.
Page 42: Power Reduction Register
ATmega48P/88P/168P/328P Power Reduction Register The Power Reduction Register (PRR), see ”PRR – Power Reduction Register” on page 45, pro- vides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock.
Page 43 ATmega48P/88P/168P/328P 7.10.5 Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consump- tion.
Page 44: Register Description
ATmega48P/88P/168P/328P 7.11 Register Description 7.11.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. 0x33 (0x53) – – – – SMCR Read/Write Initial Value • Bits 7..4 Res: Reserved Bits These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero. •...
Page 45 ATmega48P/88P/168P/328P be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to zero within four clock cycles. The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode.
Page 46: System Control And Reset
ATmega48P/88P/168P/328P 8. System Control and Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. For the ATmega168P, the instruction placed at the Reset Vector must be a JMP –...
Page 47: Power-On Reset
ATmega48P/88P/168P/328P Figure 8-1. Reset Logic DATA BUS MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out BODLEVEL [2..0] Reset Circuit Pull-up Resistor SPIKE FILTER RSTDISBL Watchdog Oscillator Delay Counters Clock Generator TIMEOUT CKSEL[3:0] SUT[1:0] Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”System and Reset Characteristics”...
Page 48: External Reset
ATmega48P/88P/168P/328P Figure 8-3. MCU Start-up, RESET Extended Externally RESET TOUT TIME-OUT INTERNAL RESET External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see ”System and Reset Characteristics” on page 320) will generate a reset, even if the clock is not running.
Page 49: Watchdog System Reset
ATmega48P/88P/168P/328P Figure 8-5. Brown-out Reset During Operation BOT+ BOT- RESET TIME-OUT TOUT INTERNAL RESET Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t .
Page 50: Watchdog Timer
ATmega48P/88P/168P/328P ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. Watchdog Timer 8.8.1 Features • Clocked from separate On-chip Oscillator •...
Page 51 ATmega48P/88P/168P/328P mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, altera- tions to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows: 1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE.
Page 52 ATmega48P/88P/168P/328P Assembly Code Example WDT_off: ; Turn off global interrupt ; Reset Watchdog Timer ; Clear WDRF in MCUSR r16, MCUSR andi r16, (0xff & (0<<WDRF)) MCUSR, r16 ; Write logical one to WDCE and WDE ; Keep old prescaler setting to prevent unintentional time-out lds r16, WDTCSR r16, (1<<WDCE) | (1<<WDE) sts WDTCSR, r16...
Page 53 ATmega48P/88P/168P/328P The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example WDT_Prescaler_Change: ; Turn off global interrupt ; Reset Watchdog Timer ; Start timed sequence lds r16, WDTCSR r16, (1<<WDCE) | (1<<WDE) sts WDTCSR, r16 ;...
Page 54: Register Description
ATmega48P/88P/168P/328P Register Description 8.9.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. 0x35 (0x55) – – – – WDRF BORF EXTRF PORF MCUSR Read/Write Initial Value See Bit Description •...
Page 55 ATmega48P/88P/168P/328P WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode.
Page 56 ATmega48P/88P/168P/328P Table 8-2. Watchdog Timer Prescale Select (Continued) Number of WDT Oscillator Typical Time-out at WDP3 WDP2 WDP1 WDP0 Cycles = 5.0V 512K (524288) cycles 4.0 s 1024K (1048576) cycles 8.0 s Reserved 8025I–AVR–02/09...
Page 57: Interrupts
ATmega48P/88P/168P/328P 9. Interrupts T h i s s e c t i o n d e s c r i b e s t h e s p e c i f i c s o f t h e i n t e r r u p t h a n d l i n g a s p e r f o r m e d i n ATmega48P/88P/168P/328P.
Page 58 ATmega48P/88P/168P/328P Table 9-1. Reset and Interrupt Vectors in ATmega48P (Continued) Vector No. Program Address Source Interrupt Definition 0x017 ANALOG COMP Analog Comparator 0x018 2-wire Serial Interface 0x019 SPM READY Store Program Memory Ready The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega48P is: Address Labels Code Comments...
Page 59: Interrupt Vectors In Atmega88P
ATmega48P/88P/168P/328P Interrupt Vectors in ATmega88P Table 9-2. Reset and Interrupt Vectors in ATmega88P Program Vector No. Address Source Interrupt Definition 0x000 RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset 0x001 INT0 External Interrupt Request 0 0x002 INT1 External Interrupt Request 1 0x003 PCINT0...
Page 60 ATmega48P/88P/168P/328P Table 9-3. Reset and Interrupt Vectors Placement in ATmega88P BOOTRST IVSEL Reset Address Interrupt Vectors Start Address 0x000 0x001 0x000 Boot Reset Address + 0x001 Boot Reset Address 0x001 Boot Reset Address Boot Reset Address + 0x001 Note: 1. The Boot Reset Address is shown in Table 24-7 on page 289.
Page 61 ATmega48P/88P/168P/328P When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88P is: Address Labels Code Comments 0x000...
Page 62: Interrupt Vectors In Atmega168P
ATmega48P/88P/168P/328P 0xC1B SPH,r16 ; Set Stack Pointer to top of RAM 0xC1C r16,low(RAMEND) 0xC1D SPL,r16 0xC1E ; Enable interrupts 0xC1F <instr> Interrupt Vectors in ATmega168P Table 9-4. Reset and Interrupt Vectors in ATmega168P Program VectorNo. Address Source Interrupt Definition 0x0000 RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset 0x0002...
Page 63 ATmega48P/88P/168P/328P Table 9-5 on page 63 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.
Page 64 ATmega48P/88P/168P/328P 0x0034 SPH,r16 ; Set Stack Pointer to top of RAM 0x0035 r16, low(RAMEND) 0x0036 SPL,r16 0x0037 ; Enable interrupts 0x0038 <instr> When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega168P is: Address Labels Code Comments...
Page 65: Interrupt Vectors In Atmega328P
ATmega48P/88P/168P/328P Address Labels Code Comments .org 0x1C00 0x1C00 RESET ; Reset handler 0x1C02 EXT_INT0 ; IRQ0 Handler 0x1C04 EXT_INT1 ; IRQ1 Handler 0x1C32 SPM_RDY ; Store Program Memory Ready Handler 0x1C33 RESET: ldi r16,high(RAMEND); Main program start 0x1C34 SPH,r16 ; Set Stack Pointer to top of RAM 0x1C35 r16,low(RAMEND) 0x1C36...
Page 66 ATmega48P/88P/168P/328P Table 9-6. Reset and Interrupt Vectors in ATmega328P (Continued) Program VectorNo. Address Source Interrupt Definition 0x002A ADC Conversion Complete 0x002C EE READY EEPROM Ready 0x002E ANALOG COMP Analog Comparator 0x0030 2-wire Serial Interface 0x0032 SPM READY Store Program Memory Ready Notes: 1.
Page 67 ATmega48P/88P/168P/328P 0x001C TIM0_COMPA ; Timer0 Compare A Handler 0x001E TIM0_COMPB ; Timer0 Compare B Handler 0x0020 TIM0_OVF ; Timer0 Overflow Handler 0x0022 SPI_STC ; SPI Transfer Complete Handler 0x0024 USART_RXC ; USART, RX Complete Handler 0x0026 USART_UDRE ; USART, UDR Empty Handler 0x0028 USART_TXC ;...
Page 68: Register Description
ATmega48P/88P/168P/328P .org 0x3C00 0x3C00 RESET: ldi r16,high(RAMEND); Main program start 0x3C01 SPH,r16 ; Set Stack Pointer to top of RAM 0x3C02 r16,low(RAMEND) 0x3C03 SPL,r16 0x3C04 ; Enable interrupts 0x3C05 <instr> When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega328P is: Address Labels Code...
Page 69 ATmega48P/88P/168P/328P a. Write the Interrupt Vector Change Enable (IVCE) bit to one. b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL.
Page 70: External Interrupts
ATmega48P/88P/168P/328P 10. External Interrupts The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled PCINT23..16 pin toggles.
Page 71: Register Description
ATmega48P/88P/168P/328P 10.2 Register Description 10.2.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. (0x69) – – – – ISC11 ISC10 ISC01 ISC00 EICRA Read/Write Initial Value • Bit 7..4 – Res: Reserved Bits These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero.
Page 72 ATmega48P/88P/168P/328P 10.2.2 EIMSK – External Interrupt Mask Register 0x1D (0x3D) – – – – – – INT1 INT0 EIMSK Read/Write Initial Value • Bit 7..2 – Res: Reserved Bits These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero. •...
Page 73 ATmega48P/88P/168P/328P 10.2.4 PCICR – Pin Change Interrupt Control Register (0x68) – – – – – PCIE2 PCIE1 PCIE0 PCICR Read/Write Initial Value • Bit 7..3 - Res: Reserved Bits These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero. •...
Page 74 ATmega48P/88P/168P/328P • Bit 0 - PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector.
Page 75: O-Ports
ATmega48P/88P/168P/328P 11. I/O-Ports 11.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when chang- ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Page 76: Ports As General Digital I/O
ATmega48P/88P/168P/328P Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 11.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 11-2 shows a func- tional description of one I/O-port pin, here generically called Pxn.
Page 77 ATmega48P/88P/168P/328P If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
Page 78 ATmega48P/88P/168P/328P Figure 11-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS in r17, PINx SYNC LATCH PINxn 0x00 0xFF pd, max pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH”...
Page 79 ATmega48P/88P/168P/328P Assembly Code Example ; Define pull-ups and set outputs high ; Define directions for port pins r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) PORTB,r16 DDRB,r17 ; Insert nop for synchronization ; Read port pins r16,PINB C Code Example unsigned char i; /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);...
Page 80: Alternate Port Functions
ATmega48P/88P/168P/328P ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset.
Page 81 ATmega48P/88P/168P/328P Table 11-2 summarizes the function of the overriding signals. The pin and port indexes from Fig- ure 11-5 on page 80 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 11-2.
Page 82 ATmega48P/88P/168P/328P 11.3.1 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 11-3. Table 11-3. Port B Pins Alternate Functions Port Pin Alternate Functions Chip Clock Oscillator pin 2 XTAL2 ( Timer Oscillator pin 2 TOSC2 ( PCINT7 (Pin Change Interrupt 7) Chip Clock Oscillator pin 1 or External clock input...
Page 83 ATmega48P/88P/168P/328P AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PB6 is dis- connected from the port, and becomes the input of the inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. PCINT6: Pin Change Interrupt source 6.
Page 84 ATmega48P/88P/168P/328P (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source. • ICP1/CLKO/PCINT0 – Port B, Bit 0 ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1.
Page 85 ATmega48P/88P/168P/328P Table 11-5. Overriding Signals for Alternate Functions in PB3..PB0 Signal PB3/MOSI/ PB2/SS/ PB1/OC1A/ PB0/ICP1/ Name OC2/PCINT3 OC1B/PCINT2 PCINT1 PCINT0 PUOE SPE • MSTR SPE • MSTR PUOV PORTB3 • PUD PORTB2 • PUD DDOE SPE • MSTR SPE • MSTR DDOV SPE •...
Page 86 ATmega48P/88P/168P/328P The alternate pin configuration is as follows: • RESET/PCINT14 – Port C, Bit 6 RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources. When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an I/O pin.
Page 87 ATmega48P/88P/168P/328P • ADC1/PCINT9 – Port C, Bit 1 PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power. PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source. •...
Page 88 ATmega48P/88P/168P/328P Table 11-8. Overriding Signals for Alternate Functions in PC3..PC0 Signal PC3/ADC3/ PC2/ADC2/ PC1/ADC1/ PC0/ADC0/ Name PCINT11 PCINT10 PCINT9 PCINT8 PUOE PUOV DDOE DDOV PVOE PVOV PCINT11 • PCIE1 + PCINT10 • PCIE1 + PCINT9 • PCIE1 + PCINT8 • PCIE1 + DIEOE ADC3D ADC2D...
Page 89 ATmega48P/88P/168P/328P The alternate pin configuration is as follows: • AIN1/OC2B/PCINT23 – Port D, Bit 7 AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.
Page 90 ATmega48P/88P/168P/328P • INT0/PCINT18 – Port D, Bit 2 INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source. PCINT18: Pin Change Interrupt source 18. The PD2 pin can serve as an external interrupt source. • TXD/PCINT17 – Port D, Bit 1 TXD, Transmit Data (Data output pin for the USART).
Page 91 ATmega48P/88P/168P/328P Table 11-11. Overriding Signals for Alternate Functions in PD3..PD0 Signal PD3/OC2B/INT1/ PD2/INT0/ PD1/TXD/ PD0/RXD/ Name PCINT19 PCINT18 PCINT17 PCINT16 PUOE TXEN RXEN PORTD0 • PUD DDOE TXEN RXEN DDOV PVOE OC2B ENABLE TXEN PVOV OC2B INT1 ENABLE + INT0 ENABLE + DIEOE PCINT17 •...
Page 92: Register Description
ATmega48P/88P/168P/328P 11.4 Register Description 11.4.1 MCUCR – MCU Control Register 0x35 (0x55) – BODS BODSE – – IVSEL IVCE MCUCR Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
Page 93 ATmega48P/88P/168P/328P 11.4.8 PORTD – The Port D Data Register 0x0B (0x2B) PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD Read/Write Initial Value 11.4.9 DDRD – The Port D Data Direction Register 0x0A (0x2A) DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD...
Page 94: 12 8-Bit Timer/Counter0 With Pwm
ATmega48P/88P/168P/328P 12. 8-bit Timer/Counter0 with PWM 12.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period •...
Page 95 ATmega48P/88P/168P/328P Figure 12-1. 8-bit Timer/Counter Block Diagram Count TOVn (Int.Req.) Clear Control Logic Clock Select Direction Edge Detector BOTTOM ( From Prescaler ) Timer/Counter TCNTn OCnA (Int.Req.) Waveform OCnA Generation OCRnA Fixed OCnB (Int.Req.) Value Waveform OCnB Generation OCRnB TCCRnA TCCRnB 12.2.1 Definitions...
Page 96: Timer/Counter Clock Sources
ATmega48P/88P/168P/328P The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected.
Page 97: Output Compare Unit
ATmega48P/88P/168P/328P The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B.
Page 98: Compare Match Output Unit
ATmega48P/88P/168P/328P The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is dis- abled the CPU will access the OCR0x directly. 12.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by...
Page 99: Modes Of Operation
ATmega48P/88P/168P/328P Figure 12-4. Compare Match Output Unit, Schematic COMnx1 Waveform COMnx0 Generator FOCn OCnx OCnx PORT The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin.
Page 100 ATmega48P/88P/168P/328P 12.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot- tom (0x00).
Page 101 ATmega48P/88P/168P/328P the pin is set to output. The waveform generated will have a maximum frequency of f /2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following clk_I/O equation: clk_I/O ------------------------------------------------- - ⋅ ⋅ OCnx OCRnx The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
Page 102 ATmega48P/88P/168P/328P In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set.
Page 103 ATmega48P/88P/168P/328P Figure 12-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value.
Page 104: Timer/Counter Timing Diagrams
ATmega48P/88P/168P/328P symmetry around BOTTOM the OCnx value at MAX must correspond to the result of an up- counting Compare Match. • The timer starts counting from a value higher than the one in OCRnx, and for that reason misses the Compare Match and hence the OCnx change that would have happened on the way up.
Page 105 ATmega48P/88P/168P/328P Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk_I/O (clk TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 12-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP.
Page 106: Register Description
ATmega48P/88P/168P/328P 12.9 Register Description 12.9.1 TCCR0A – Timer/Counter Control Register A 0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to.
Page 107 ATmega48P/88P/168P/328P Table 12-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor- rect PWM mode. Table 12-4. Compare Output Mode, Phase Correct PWM Mode COM0A1 COM0A0 Description Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match.
Page 108 ATmega48P/88P/168P/328P Table 12-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor- rect PWM mode. Table 12-7. Compare Output Mode, Phase Correct PWM Mode COM0B1 COM0B0 Description Normal port operation, OC0B disconnected. Reserved Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting.
Page 109 ATmega48P/88P/168P/328P 12.9.2 TCCR0B – Timer/Counter Control Register B 0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
Page 110 ATmega48P/88P/168P/328P Table 12-9. Clock Select Bit Description CS02 CS01 CS00 Description No clock source (Timer/Counter stopped) /(No prescaling) /8 (From prescaler) /64 (From prescaler) /256 (From prescaler) /1024 (From prescaler) External clock source on T0 pin. Clock on falling edge. External clock source on T0 pin.
Page 111 ATmega48P/88P/168P/328P 12.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register (0x6E) – – – – – OCIE0B OCIE0A TOIE0 TIMSK0 Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATmega48P/88P/168P/328P and will always read as zero. •...
Page 112 ATmega48P/88P/168P/328P • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
Page 113: 16-Bit Timer/Counter1 With Pwm
ATmega48P/88P/168P/328P 13. 16-bit Timer/Counter1 with PWM 13.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on Compare Match (Auto Reload) •...
Page 114 ATmega48P/88P/168P/328P Figure 13-1. 16-bit Timer/Counter Block Diagram Count TOVn (Int.Req.) Clear Control Logic Clock Select Direction Edge Detector BOTTOM ( From Prescaler ) Timer/Counter TCNTn OCnA (Int.Req.) Waveform OCnA Generation OCRnA OCnB Fixed (Int.Req.) Values Waveform OCnB Generation OCRnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge...
Page 115: Accessing 16-Bit Registers
ATmega48P/88P/168P/328P put Compare Units” on page 122. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See ”Analog Comparator”...
Page 116 ATmega48P/88P/168P/328P Assembly Code Examples ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H C Code Examples unsigned int i; /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1;...
Page 117 ATmega48P/88P/168P/328P Assembly Code Example TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 C Code Example unsigned int TIM16_ReadTCNT1( void ) unsigned char sreg; unsigned int i;...
Page 118: Timer/Counter Clock Sources
ATmega48P/88P/168P/328P Assembly Code Example TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 C Code Example void TIM16_WriteTCNT1( unsigned int i ) unsigned char sreg;...
Page 119: Counter Unit
ATmega48P/88P/168P/328P 13.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 13-2 shows a block diagram of the counter and its surroundings. Figure 13-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select...
Page 120: Input Capture Unit
ATmega48P/88P/168P/328P The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 13.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence.
Page 121 ATmega48P/88P/168P/328P tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to ”Accessing 16-bit Registers”...
Page 122: Output Compare Units
ATmega48P/88P/168P/328P cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 13.7 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x).
Page 123 ATmega48P/88P/168P/328P prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out- put glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is dis- abled the CPU will access the OCR1x directly.
Page 124: Compare Match Output Unit
ATmega48P/88P/168P/328P 13.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 13-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting.
Page 125: Modes Of Operation
ATmega48P/88P/168P/328P non-PWM modes refer to Table 13-1 on page 134. For fast PWM mode refer to Table 13-2 on page 135, and for phase correct and phase and frequency correct PWM refer to Table 13-3 on page 135. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written.
Page 126 ATmega48P/88P/168P/328P Figure 13-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (COMnA1:0 = 1) (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value.
Page 127 ATmega48P/88P/168P/328P The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max- imum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: ---------------------------------- - 2 ( )
Page 128 ATmega48P/88P/168P/328P to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set.
Page 129 ATmega48P/88P/168P/328P 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: ---------------------------------- - 2 ( ) PCPWM In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11).
Page 130 ATmega48P/88P/168P/328P implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output.
Page 131 ATmega48P/88P/168P/328P the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: ---------------------------------- - 2 ( ) PFCPWM In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9).
Page 132: Timer/Counter Timing Diagrams
ATmega48P/88P/168P/328P Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature.
Page 133 ATmega48P/88P/168P/328P Figure 13-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk_I/O (clk TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 13-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM.
Page 134: Register Description
ATmega48P/88P/168P/328P Figure 13-13 shows the same timing data, but with the prescaler enabled. Figure 13-13. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O (clk TCNTn TOP - 1 BOTTOM BOTTOM + 1 (CTC and FPWM) TCNTn TOP - 1 TOP - 1 TOP - 2 (PC and PFC PWM) TOVn...
Page 135 ATmega48P/88P/168P/328P Table 13-2 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 13-2. Compare Output Mode, Fast PWM COM1A1/COM1B1 COM1A0/COM1B0 Description Normal port operation, OC1A/OC1B disconnected. WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation).
Page 136 ATmega48P/88P/168P/328P Table 13-4. Waveform Generation Mode Bit Description WGM12 WGM11 WGM10 Timer/Counter Mode of Update of TOV1 Flag Mode WGM13 (CTC1) (PWM11) (PWM10) Operation OCR1 Set on Normal 0xFFFF Immediate PWM, Phase Correct, 8-bit 0x00FF BOTTOM PWM, Phase Correct, 9-bit 0x01FF BOTTOM PWM, Phase Correct, 10-bit...
Page 137 ATmega48P/88P/168P/328P When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use.
Page 138 ATmega48P/88P/168P/328P 13.11.4 TCNT1H and TCNT1L – Timer/Counter1 (0x85) TCNT1[15:8] TCNT1H (0x84) TCNT1[7:0] TCNT1L Read/Write Initial Value The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP).
Page 139 ATmega48P/88P/168P/328P 13.11.7 ICR1H and ICR1L – Input Capture Register 1 (0x87) ICR1[15:8] ICR1H (0x86) ICR1[7:0] ICR1L Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value.
Page 140 ATmega48P/88P/168P/328P 13.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register 0x16 (0x36) – – ICF1 – – OCF1B OCF1A TOV1 TIFR1 Read/Write Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero. •...
Page 141: Timer/Counter0 And Timer/Counter1 Prescalers
ATmega48P/88P/168P/328P 14. Timer/Counter0 and Timer/Counter1 Prescalers ”8-bit Timer/Counter0 with PWM” on page 94 ”16-bit Timer/Counter1 with PWM” on page share the same prescaler module, but the Timer/Counters can have different prescaler set- tings. The description below applies to both Timer/Counter1 and Timer/Counter0. 14.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
Page 142 ATmega48P/88P/168P/328P Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling.
Page 143: Register Description
ATmega48P/88P/168P/328P 14.4 Register Description 14.4.1 GTCCR – General Timer/Counter Control Register 0x23 (0x43) – – – – – PSRASY PSRSYNC GTCCR Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond- ing prescaler reset signals asserted.
Page 144: 15 8-Bit Timer/Counter2 With Pwm And Asynchronous Operation
ATmega48P/88P/168P/328P 15. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 15.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B) •...
Page 145: Timer/Counter Clock Sources
ATmega48P/88P/168P/328P 15.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2).
Page 146: Output Compare Unit
ATmega48P/88P/168P/328P Figure 15-2. Counter Unit Block Diagram TOVn DATA BUS (Int.Req.) TOSC1 count clear Oscillator TCNTn Control Logic Prescaler direction TOSC2 bottom Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero).
Page 147 ATmega48P/88P/168P/328P Figure 15-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn (8-bit Comparator ) OCFnx (Int.Req.) bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
Page 148: Compare Match Output Unit
ATmega48P/88P/168P/328P The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com- pare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when changing between Waveform Generation modes.
Page 149: Modes Of Operation
ATmega48P/88P/168P/328P 15.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the OC2x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 15-5 on page 159.
Page 150 ATmega48P/88P/168P/328P Figure 15-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 1) (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
Page 151 ATmega48P/88P/168P/328P In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 15-6.
Page 152 ATmega48P/88P/168P/328P generated will have a maximum frequency of f /2 when OCR2A is set to zero. This fea- clk_I/O ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 15.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct...
Page 153: Timer/Counter Timing Diagrams
ATmega48P/88P/168P/328P output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See Table 15-4 on page 159). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x Register at compare match between OCR2x and TCNT2 when the counter decrements.
Page 154 ATmega48P/88P/168P/328P Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O (clk TCNTn MAX - 1 BOTTOM BOTTOM + 1 TOVn Figure 15-10 shows the setting of OCF2A in all modes except CTC mode. Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f clk_I/O (clk TCNTn...
Page 155: Asynchronous Operation Of Timer/Counter2
ATmega48P/88P/168P/328P 15.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: a.
Page 156: Timer/Counter Prescaler
ATmega48P/88P/168P/328P • Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value.
Page 157 ATmega48P/88P/168P/328P (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. For Timer/Counter2, the possible prescaled selections are: clk /8, clk /32, clk...
Page 158: Register Description
ATmega48P/88P/168P/328P 15.11 Register Description 15.11.1 TCCR2A – Timer/Counter Control Register A (0xB0) COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 TCCR2A Read/Write Initial Value • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to.
Page 159 ATmega48P/88P/168P/328P Table 15-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor- rect PWM mode. Table 15-4. Compare Output Mode, Phase Correct PWM Mode COM2A1 COM2A0 Description Normal port operation, OC2A disconnected. WGM22 = 0: Normal Port Operation, OC2A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match.
Page 160 ATmega48P/88P/168P/328P Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at BOTTOM. See ”Phase Correct PWM Mode” on page 152 for more details.
Page 161 ATmega48P/88P/168P/328P 15.11.2 TCCR2B – Timer/Counter Control Register B (0xB1) FOC2A FOC2B – – WGM22 CS22 CS21 CS20 TCCR2B Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode.
Page 162 ATmega48P/88P/168P/328P Table 15-9. Clock Select Bit Description CS22 CS21 CS20 Description No clock source (Timer/Counter stopped). /(No prescaling) /8 (From prescaler) /32 (From prescaler) /64 (From prescaler) /128 (From prescaler) /256 (From prescaler) /1024 (From prescaler) If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output.
Page 163 ATmega48P/88P/168P/328P 15.11.6 TIMSK2 – Timer/Counter2 Interrupt Mask Register (0x70) – – – – – OCIE2B OCIE2A TOIE2 TIMSK2 Read/Write Initial Value • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled.
Page 164 ATmega48P/88P/168P/328P 15.11.8 ASSR – Asynchronous Status Register (0xB6) – EXCLK TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB ASSR Read/Write Initial Value • Bit 7 – RES: Reserved bit This bit is reserved and will always read as zero. • Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buf- fer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal.
Page 165 ATmega48P/88P/168P/328P The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 15.11.9 GTCCR – General Timer/Counter Control Register 0x23 (0x43) –...
Page 166: Spi - Serial Peripheral Interface
ATmega48P/88P/168P/328P 16. SPI – Serial Peripheral Interface 16.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection •...
Page 167 ATmega48P/88P/168P/328P The interconnection between Master and Slave CPUs with SPI is shown in Figure 16-2 on page 167. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
Page 168 ATmega48P/88P/168P/328P When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 16-1 on page 168. For more details on automatic port overrides, refer to ”Alternate Port Functions” on page (Note:) Table 16-1.
Page 169 ATmega48P/88P/168P/328P Assembly Code Example SPI_MasterInit: ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) SPCR,r17 SPI_MasterTransmit: ; Start transmission of data (r16) SPDR,r16 Wait_Transmit: ; Wait for transmission complete r16, SPSR sbrsr16, SPIF rjmp Wait_Transmit...
Page 170 ATmega48P/88P/168P/328P The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input r17,(1<<DD_MISO) DDR_SPI,r17 ; Enable SPI r17,(1<<SPE) SPCR,r17 SPI_SlaveReceive: ;...
Page 171: Ss Pin Functionality
ATmega48P/88P/168P/328P 16.3 SS Pin Functionality 16.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs.
Page 172 ATmega48P/88P/168P/328P Figure 16-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN MSB first (DORD = 0) Bit 6 Bit 5 Bit 4 Bit 3...
Page 173: Register Description
ATmega48P/88P/168P/328P 16.5 Register Description 16.5.1 SPCR – SPI Control Register 0x2C (0x4C) SPIE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
Page 174 ATmega48P/88P/168P/328P • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f shown in the following table: Table 16-5.
Page 175 ATmega48P/88P/168P/328P 16.5.3 SPDR – SPI Data Register 0x2E (0x4E) SPDR Read/Write Initial Value Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read.
Page 176: Usart0
ATmega48P/88P/168P/328P 17. USART0 17.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits •...
Page 177: Clock Generation
ATmega48P/88P/168P/328P Figure 17-1. USART Block Diagram Clock Generator UBRRn [H:L] BAUD RATE GENERATOR SYNC LOGIC XCKn CONTROL Transmitter UDRn(Transmit) CONTROL PARITY GENERATOR TRANSMIT SHIFT REGISTER TxDn CONTROL Receiver CLOCK RECOVERY CONTROL DATA RECEIVE SHIFT REGISTER RxDn RECOVERY CONTROL PARITY UDRn (Receive) CHECKER UCSRnA UCSRnB...
Page 178 ATmega48P/88P/168P/328P Figure 17-2 shows a block diagram of the clock generation logic. Figure 17-2. Clock Generation Logic, Block Diagram UBRRn U2Xn foscn UBRRn+1 Prescaling Down-Counter txclk DDR_XCKn Sync Edge Register Detector xcki UMSELn XCKn xcko DDR_XCKn UCPOLn rxclk Signal description: txclk Transmitter clock (Internal Signal).
Page 179 ATmega48P/88P/168P/328P Table 17-1 contains equations for calculating the baud rate (in bits per second) and for calculat- ing the UBRRn value for each mode of operation using an internally generated clock source. Table 17-1. Equations for Calculating Baud Rate Register Setting Equation for Calculating Baud Equation for Calculating Operating Mode...
Page 180: Frame Formats
ATmega48P/88P/168P/328P 17.3.3 External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 17-2 for details. External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability.
Page 181 ATmega48P/88P/168P/328P A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Page 182: Usart Initialization
ATmega48P/88P/168P/328P 17.5 USART Initialization The USART has to be initialized before any communication can take place. The initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization.
Page 183: Data Transmission - The Usart Transmitter
ATmega48P/88P/168P/328P For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly Code Example USART_Init: ; Set baud rate UBRRnH, r17 UBRRnL, r16 ; Enable receiver and transmitter r16, (1<<RXENn)|(1<<TXENn) UCSRnB,r16 ; Set frame format: 8data, 2stop bit r16, (1<<USBSn)|(3<<UCSZn0) UCSRnC,r16 C Code Example...
Page 184 ATmega48P/88P/168P/328P chronous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. 17.6.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location.
Page 185 ATmega48P/88P/168P/328P show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16. (1)(2) Assembly Code Example USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ;...
Page 186: Data Reception - The Usart Receiver
ATmega48P/88P/168P/328P UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer.
Page 187 ATmega48P/88P/168P/328P bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ;...
Page 188 ATmega48P/88P/168P/328P Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer r18, UCSRnA r17, UCSRnB r16, UDRn ; If error, return -1 andi r18,(1<<FEn)|(1<<DORn)|(1<<UPEn) breq USART_ReceiveNoError r17, HIGH(-1) r16, LOW(-1)
Page 189 ATmega48P/88P/168P/328P 17.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data).
Page 190: Asynchronous Data Reception
ATmega48P/88P/168P/328P The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 17.7.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate.
Page 191 ATmega48P/88P/168P/328P Figure 17-5. Start Bit Sampling IDLE START BIT 0 Sample (U2X = 0) Sample (U2X = 1) When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
Page 192 ATmega48P/88P/168P/328P Figure 17-7. Stop Bit Sampling and Next Start Bit Sampling STOP 1 Sample (U2X = 0) Sample (U2X = 1) The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
Page 193: Multi-Processor Communication Mode
ATmega48P/88P/168P/328P Table 17-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) Recommended Max # (Data+Parity Bit) Max Total Error (%) Receiver Error (%) slow fast 93.20 106.67 +6.67/-6.8 ± 3.0 94.12 105.79 +5.79/-5.88 ± 2.5 94.81 105.11 +5.11/-5.19...
Page 194 ATmega48P/88P/168P/328P nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU.
Page 195: Register Description
ATmega48P/88P/168P/328P 17.10 Register Description 17.10.1 UDRn – USART I/O Data Register n RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg- ister (TXB) will be the destination for data written to the UDRn Register location.
Page 196 ATmega48P/88P/168P/328P Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero.
Page 197 ATmega48P/88P/168P/328P • Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set.
Page 198 ATmega48P/88P/168P/328P • Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Page 199: Examples Of Baud Rate Setting
ATmega48P/88P/168P/328P Table 17-8. UCPOLn Bit Settings Transmitted Data Changed (Output of Received Data Sampled (Input on RxDn UCPOLn TxDn Pin) Pin) Rising XCKn Edge Falling XCKn Edge Falling XCKn Edge Rising XCKn Edge 17.10.5 UBRRnL and UBRRnH – USART Baud Rate Registers –...
Page 200 ATmega48P/88P/168P/328P Table 17-9. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies = 1.0000 MHz = 1.8432 MHz = 2.0000 MHz Baud U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn...
Page 201 ATmega48P/88P/168P/328P Table 17-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) = 3.6864 MHz = 4.0000 MHz = 7.3728 MHz Baud U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn...
Page 202 ATmega48P/88P/168P/328P Table 17-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) 11.0592 = 8.0000 MHz = 14.7456 MHz Baud U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error...
Page 203 ATmega48P/88P/168P/328P Table 17-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) = 16.0000 MHz = 18.4320 MHz = 20.0000 MHz Baud U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn...
Page 204: Usart In Spi Mode
ATmega48P/88P/168P/328P 18. USART in SPI Mode 18.1 Features • Full Duplex, Three-wire Synchronous Data Transfer • Master Operation • Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3) • LSB First or MSB First Data Transfer (Configurable Data Order) •...
Page 205: Spi Data Modes And Timing
ATmega48P/88P/168P/328P Table 18-1. Equations for Calculating Baud Rate Register Setting Equation for Calculating Baud Equation for Calculating UBRRn Operating Mode Rate Value Synchronous Master ------------------- - 1 BAUD -------------------------------------- - UBRRn – mode 2 UBRRn 2BAUD Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps) BAUD Baud rate (in bits per second, bps) System Oscillator clock frequency...
Page 206: Frame Formats
ATmega48P/88P/168P/328P Figure 18-1. UCPHAn and UCPOLn data transfer timing diagrams. UCPOL=0 UCPOL=1 Data setup (TXD) Data setup (TXD) Data sample (RXD) Data sample (RXD) Data setup (TXD) Data setup (TXD) Data sample (RXD) Data sample (RXD) 18.5 Frame Formats A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid frame formats: •...
Page 207 ATmega48P/88P/168P/328P be used to check that there are no unread data in the receive buffer. Note that the TXCn Flag must be cleared before each transmission (before UDRn is written) if it is used for this purpose. The following simple USART initialization code examples show one assembly and one C func- tion that are equal in functionality.
Page 208: Data Transfer
ATmega48P/88P/168P/328P 18.6 Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.
Page 209 ATmega48P/88P/168P/328P Assembly Code Example USART_MSPIM_Transfer: ; Wait for empty transmit buffer sbis UCSRnA, UDREn rjmp USART_MSPIM_Transfer ; Put data (r16) into buffer, sends the data out UDRn,r16 ; Wait for data to be received USART_MSPIM_Wait_RXCn: sbis UCSRnA, RXCn rjmp USART_MSPIM_Wait_RXCn ;...
Page 210: Avr Usart Mspim Vs. Avr Spi
ATmega48P/88P/168P/328P 18.7 AVR USART MSPIM vs. AVR SPI The USART in MSPIM mode is fully compatible with the AVR SPI regarding: • Master mode timing diagram. • The UCPOLn bit functionality is identical to the SPI CPOL bit. • The UCPHAn bit functionality is identical to the SPI CPHA bit. •...
Page 211: Register Description
ATmega48P/88P/168P/328P 18.8 Register Description The following section describes the registers used for SPI operation using the USART. 18.8.1 UDRn – USART MSPIM I/O Data Register The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART operation.
Page 212 ATmega48P/88P/168P/328P • Bit 6 - TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set.
Page 213 ATmega48P/88P/168P/328P • Bit 5:3 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnC is written. • Bit 2 - UDORDn: Data Order When set to one the LSB of the data word is transmitted first.
Page 214: 19 2-Wire Serial Interface
ATmega48P/88P/168P/328P 19. 2-wire Serial Interface 19.1 Features • Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space Allows up to 128 Different Slave Addresses •...
Page 215 ATmega48P/88P/168P/328P 19.2.1 TWI Terminology The following definitions are frequently encountered in this section. Table 19-1. TWI Terminology Term Description The device that initiates and terminates a transmission. The Master also generates the Master SCL clock. Slave The device addressed by a Master. Transmitter The device placing data on the bus.
Page 216: Data Transfer And Frame Format
ATmega48P/88P/168P/328P 19.3 Data Transfer and Frame Format 19.3.1 Transferring Bits Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high. The only exception to this rule is for generating start and stop conditions.
Page 217 ATmega48P/88P/168P/328P 19.3.3 Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read opera- tion is to be performed, otherwise a write operation should be performed. When a Slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle.
Page 218: Multi-Master Bus Systems, Arbitration And Synchronization
ATmega48P/88P/168P/328P Figure 19-5. Data Packet Format Data MSB Data LSB Aggregate SDA from Transmitter SDA from Receiver SCL from Master STOP, REPEATED SLA+R/W Data Byte START or Next Data Byte 19.3.5 Combining Address and Data Packets into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition.
Page 219 ATmega48P/88P/168P/328P masters have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted. • Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion.
Page 220 ATmega48P/88P/168P/328P Figure 19-8. Arbitration Between Two Masters START Master A Loses Arbitration, SDA SDA from Master A SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit. •...
Page 221: Overview Of The Twi Module
ATmega48P/88P/168P/328P 19.5 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 19-9. All registers drawn in a thick line are accessible through the AVR data bus. Figure 19-9. Overview of the TWI Module Slew-rate Spike Slew-rate...
Page 222 ATmega48P/88P/168P/328P that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is generated according to the following equation: CPU Clock frequency SCL frequency ---------------------------------------------------------------------------------------- - ⋅ 2(TWBR) PrescalerValue • TWBR = Value of the TWI Bit Rate Register. •...
Page 223: Using The Twi
ATmega48P/88P/168P/328P able. As long as the TWINT Flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue. The TWINT Flag is set in the following situations: •...
Page 224 ATmega48P/88P/168P/328P Figure 19-10. Interfacing the Application to the TWI in a Typical Transmission 3. Check TWSR to see if START was 5. Check TWSR to see if SLA+W was 1. Application 7. Check TWSR to see if data was sent sent.
Page 225 ATmega48P/88P/168P/328P not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet. 6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has successfully been sent.
Page 226 ATmega48P/88P/168P/328P Assembly Code Example C Example Comments r16, TWCR = (1<<TWINT)|(1<<TWSTA)| (1<<TWINT)|(1<<TWSTA)| (1<<TWEN) Send START condition (1<<TWEN) TWCR, r16 wait1: while (!(TWCR & (1<<TWINT))) Wait for TWINT Flag set. This r16,TWCR indicates that the START sbrs r16,TWINT condition has been transmitted rjmp wait1 r16,TWSR if ((TWSR &...
Page 227: Transmission Modes
ATmega48P/88P/168P/328P 19.7 Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM.
Page 228 ATmega48P/88P/168P/328P Figure 19-11. Data Transfer in Master Transmitter Mode Device 1 Device 2 ..Device 3 Device n MASTER SLAVE TRANSMITTER RECEIVER A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –...
Page 229 ATmega48P/88P/168P/328P After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with- out losing control of the bus.
Page 230 ATmega48P/88P/168P/328P Figure 19-12. Formats and States in the Master Transmitter Mode Successfull DATA transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave Other master Other master...
Page 231 ATmega48P/88P/168P/328P Figure 19-13. Data Transfer in Master Receiver Mode Device 1 Device 2 ..Device 3 Device n MASTER SLAVE RECEIVER TRANSMITTER A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –...
Page 232 ATmega48P/88P/168P/328P the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with- out losing control over the bus. Table 19-3. Status codes for Master Receiver Mode Status Code Application Software Response (TWSR) Status of the 2-wire Serial Bus To TWCR Prescaler Bits and 2-wire Serial Interface...
Page 233 ATmega48P/88P/168P/328P Figure 19-14. Formats and States in the Master Receiver Mode Successfull DATA DATA reception from a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave Other master Other master A or A address or data byte...
Page 234 ATmega48P/88P/168P/328P To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE value Device’s Own Slave Address The upper 7 bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master.
Page 235 ATmega48P/88P/168P/328P Table 19-4. Status Codes for Slave Receiver Mode Status Code Application Software Response (TWSR) Status of the 2-wire Serial Bus To TWCR Prescaler Bits and 2-wire Serial Interface Hard- To/from TWDR TWIN are 0 ware Next Action Taken by TWI Hardware 0x60 Own SLA+W has been received;...
Page 236 ATmega48P/88P/168P/328P Figure 19-16. Formats and States in the Slave Receiver Mode Reception of the own DATA DATA P or S slave address and one or more data bytes. All are acknowledged Last data byte received P or S is not acknowledged Arbitration lost as master and addressed as slave Reception of the general call...
Page 237 ATmega48P/88P/168P/328P To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE value Device’s Own Slave Address The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master.
Page 238 ATmega48P/88P/168P/328P Table 19-5. Status Codes for Slave Transmitter Mode Status Code Application Software Response (TWSR) Status of the 2-wire Serial Bus To TWCR Prescaler and 2-wire Serial Interface Hard- To/from TWDR TWIN Bits ware Next Action Taken by TWI Hardware are 0 0xA8 Own SLA+R has been received;...
Page 239 ATmega48P/88P/168P/328P Figure 19-18. Formats and States in the Slave Transmitter Mode Reception of the own DATA DATA P or S slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. All 1's P or S Switched to not addressed...
Page 240: Multi-Master Systems And Arbitration
ATmega48P/88P/168P/328P Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed.
Page 241: Register Description
ATmega48P/88P/168P/328P • Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master.
Page 242 ATmega48P/88P/168P/328P • Bit 7 – TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector.
Page 243 ATmega48P/88P/168P/328P • Bit 0 – TWIE: TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti- vated for as long as the TWINT Flag is high. 19.9.3 TWSR –...
Page 244 ATmega48P/88P/168P/328P of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly. • Bits 7..0 – TWD: TWI Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire Serial Bus.
Page 245 ATmega48P/88P/168P/328P Figure 19-22. TWI Address Match Logic, Block Diagram TWAR0 Address Match Address Bit 0 TWAMR0 Address Bit Comparator 0 Address Bit Comparator 6..1 • Bit 0 – Res: Reserved Bit This bit is an unused bit in the ATmega48P/88P/168P/328P, and will always read as zero. 8025I–AVR–02/09...
Page 246: Analog Comparator
ATmega48P/88P/168P/328P 20. Analog Comparator 20.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function.
Page 247: Register Description
ATmega48P/88P/168P/328P Table 20-1. Analog Comparator Multiplexed Input ACME ADEN MUX2..0 Analog Comparator Negative Input AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 20.3 Register Description 20.3.1 ADCSRB – ADC Control and Status Register B (0x7B) – ACME – –...
Page 248 ATmega48P/88P/168P/328P certain time for the voltage to stabilize. If not stabilized, the first conversion may give a wrong value. See ”Internal Voltage Reference” on page 49 • Bit 5 – ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles.
Page 249 ATmega48P/88P/168P/328P 20.3.3 DIDR1 – Digital Input Disable Register 1 (0x7F) – – – – – – AIN1D AIN0D DIDR1 Read/Write Initial Value • Bit 7..2 – Res: Reserved Bits These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero. •...
Page 250: Analog-To-Digital Converter
ATmega48P/88P/168P/328P 21. Analog-to-Digital Converter 21.1 Features • 10-bit Resolution • 0.5 LSB Integral Non-linearity • ± 2 LSB Absolute Accuracy • 13 - 260 µs Conversion Time • Up to 76.9 kSPS (Up to 15 kSPS at Maximum Resolution) • 6 Multiplexed Single Ended Input Channels •...
Page 251 ATmega48P/88P/168P/328P Figure 21-1. Analog to Digital Converter Block Schematic Operation, ADC CONVERSION COMPLETE IRQ 8-BIT DATA BUS ADC MULTIPLEXER ADC CTRL. & STATUS ADC DATA REGISTER SELECT (ADMUX) REGISTER (ADCSRA) (ADCH/ADCL) MUX DECODER PRESCALER CONVERSION LOGIC AVCC INTERNAL 1.1V REFERENCE SAMPLE &...
Page 252: Starting A Conversion
ATmega48P/88P/168P/328P read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.
Page 253: Prescaling And Conversion Timing
ATmega48P/88P/168P/328P If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. 21.4 Prescaling and Conversion Timing Figure 21-3.
Page 254 ATmega48P/88P/168P/328P In Free Running mode, a new conversion will be started immediately after the conversion com- pletes, while ADSC remains high. For a summary of conversion times, see Table 21-1 on page 255. Figure 21-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) Next First Conversion Conversion...
Page 255: Changing Channel Or Reference Selection
ATmega48P/88P/168P/328P Figure 21-7. ADC Timing Diagram, Free Running Conversion One Conversion Next Conversion Cycle Number ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update Table 21-1. ADC Conversion Time Sample &...
Page 256: Adc Noise Canceler
ATmega48P/88P/168P/328P 21.5.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The chan- nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.
Page 257 ATmega48P/88P/168P/328P 21.6.1 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 21-8. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard- less of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path).
Page 258 ATmega48P/88P/168P/328P and ADC5) will only affect the conversion on ADC4 and ADC5 and not the other ADC channels. Figure 21-9. ADC Power Connections PC1 (ADC1) PC0 (ADC0) ADC7 AREF ADC6 AVCC 21.6.3 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V in 2 steps (LSBs).
Page 259 ATmega48P/88P/168P/328P Figure 21-10. Offset Error Output Code Ideal ADC Actual ADC Offset Error Input Voltage • Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 Figure 21-11.
Page 260 ATmega48P/88P/168P/328P Figure 21-12. Integral Non-linearity (INL) Output Code Ideal ADC Actual ADC Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 21-13.
Page 261: Adc Conversion Result
ATmega48P/88P/168P/328P 21.7 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is ⋅ 1024 -------------------------- where V is the voltage on the selected input pin and V the selected voltage reference (see Table 21-3 on page 262 Table 21-4 on page...
Page 262: Register Description
ATmega48P/88P/168P/328P 21.9 Register Description 21.9.1 ADMUX – ADC Multiplexer Selection Register (0x7C) REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 ADMUX Read/Write Initial Value • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 21-3.
Page 263 ATmega48P/88P/168P/328P Table 21-4. Input Channel Selections MUX3..0 Single Ended Input 0000 ADC0 0001 ADC1 0010 ADC2 0011 ADC3 0100 ADC4 0101 ADC5 0110 ADC6 0111 ADC7 1000 ADC8 1001 (reserved) 1010 (reserved) 1011 (reserved) 1100 (reserved) 1101 (reserved) 1110 1.1V (V 1111 0V (GND) Note:...
Page 264 ATmega48P/88P/168P/328P • Bit 5 – ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con- version on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB.
Page 265 ATmega48P/88P/168P/328P 21.9.3 ADCL and ADCH – The ADC Data Register 21.9.3.1 ADLAR = 0 (0x79) – – – – – – ADC9 ADC8 ADCH (0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL Read/Write Initial Value 21.9.3.2 ADLAR = 1 (0x79) ADC9 ADC8...
Page 266 ATmega48P/88P/168P/328P trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set Table 21-6. ADC Auto Trigger Source Selections ADTS2 ADTS1 ADTS0...
Page 267: Debugwire On-Chip Debug System
ATmega48P/88P/168P/328P 22. debugWIRE On-chip Debug System 22.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs) •...
Page 268: Software Break Points
ATmega48P/88P/168P/328P When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor is not required for debugWIRE functionality. •...
Page 269: Self-Programming The Flash, Atmega48P
ATmega48P/88P/168P/328P 23. Self-Programming the Flash, ATmega48P 23.1 Overview In ATmega48P, there is no Read-While-Write support, and no separate Boot Loader Section. The SPM instruction can be executed from the entire Flash. The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself.
Page 270: Addressing The Flash During Self-Programming
ATmega48P/88P/168P/328P If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 23.1.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
Page 271 ATmega48P/88P/168P/328P 23.2.1 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register.
Page 272 ATmega48P/88P/168P/328P 23.2.3 Preventing Flash Corruption During periods of low V , the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied.
Page 273 ATmega48P/88P/168P/328P 23.2.5 Simple Assembly Code Example for a Boot Loader Note that the RWWSB bit will always be read as zero in ATmega48P. Nevertheless, it is recom- mended to check this bit as shown in the code example, to ensure compatibility with devices supporting Read-While-Write.
Page 274 ATmega48P/88P/168P/328P sbci YH, high(PAGESIZEB) Rdloop: r0, Z+ r1, Y+ cpse r0, r1 rjmp Error sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256 brne Rdloop ; return to RWW section ; verify that RWW section is safe to read Return: temp1, SPMCSR sbrs temp1, RWWSB ;...
Page 275: Register Description
ATmega48P/88P/168P/328P 23.3 Register Description’ 23.3.1 SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to con- trol the Program memory operations. 0x37 (0x57) SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS...
Page 276 ATmega48P/88P/168P/328P • Bit 0 – SELFPRGEN: Self Programming Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT, or PGERS, the following SPM instruction will have a spe- cial meaning, see description above.
Page 277: Boot Loader Support - Read-While-Write Self-Programming, Atmega88P, Atmega168P And Atmega328P
ATmega48P/88P/168P/328P 24. Boot Loader Support – Read-While-Write Self-Programming, ATmega88P, ATmega168P and ATmega328P 24.1 Features • Read-While-Write Self-Programming • Flexible Boot Memory Size • High Security (Separate Boot Lock Bits for a Flexible Protection) • Separate Fuse to Select Reset Vector •...
Page 278: Read-While-Write And No Read-While-Write Flash Sections
ATmega48P/88P/168P/328P 24.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft- ware update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While- Write (NRWW) section.
Page 279 ATmega48P/88P/168P/328P Figure 24-1. Read-While-Write vs. No Read-While-Write Read-While-Write (RWW) Section Z-pointer Addresses NRWW Section Z-pointer Addresses RWW No Read-While-Write (NRWW) Section Section CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation 8025I–AVR–02/09...
Page 280: Boot Loader Lock Bits
ATmega48P/88P/168P/328P Figure 24-2. Memory Sections Program Memory Program Memory BOOTSZ = '10' BOOTSZ = '11' 0x0000 0x0000 Application Flash Section Application Flash Section End RWW End RWW Start NRWW Start NRWW Application Flash Section Application Flash Section End Application End Application Start Boot Loader Boot Loader Flash Section Start Boot Loader...
Page 281: Entering The Boot Loader Program
ATmega48P/88P/168P/328P Table 24-2. Boot Lock Bit0 Protection Modes (Application Section) BLB0 Mode BLB02 BLB01 Protection No restrictions for SPM or LPM accessing the Application section. SPM is not allowed to write to the Application section. SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
Page 282: Addressing The Flash During Self-Programming
ATmega48P/88P/168P/328P 24.7 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. ZH (R31) ZL (R30) Since the Flash is organized in pages (see Table 25-11 on page 299), the Program Counter can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages.
Page 283 ATmega48P/88P/168P/328P Alternative 1, fill the buffer before a Page Erase • Fill temporary page buffer • Perform a Page Erase • Perform a Page Write Alternative 2, fill the buffer after Page Erase • Perform a Page Erase • Fill temporary page buffer •...
Page 284 ATmega48P/88P/168P/328P 24.8.4 Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SELFPRGEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading.
Page 285 ATmega48P/88P/168P/328P instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles.
Page 286 ATmega48P/88P/168P/328P Table 24-5. Signature Row Addressing Signature Byte Z-Pointer Address Device Signature Byte 1 0x0000 Device Signature Byte 2 0x0002 Device Signature Byte 3 0x0004 RC Oscillator Calibration Byte 0x0001 Note: All other addresses are reserved for future use. 24.8.11 Preventing Flash Corruption During periods of low V , the Flash program can be corrupted because the supply voltage is...
Page 287 ATmega48P/88P/168P/328P ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ;...
Page 288 ATmega48P/88P/168P/328P sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ; re-enable the RWW section spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN) call Do_spm rjmp Return Do_spm: ; check for previous SPM complete Wait_spm: temp1, SPMCSR sbrc temp1, SELFPRGEN rjmp Wait_spm ;...
Page 289 ATmega48P/88P/168P/328P 24.8.14 ATmega88P Boot Loader Parameters Table 24-7 through Table 24-9, the parameters used in the description of the self programming are given. Table 24-7. Boot Size Configuration, ATmega88P Boot Application Loader Boot Flash Flash Application Boot Reset Address (Start Boot Loader BOOTSZ1 BOOTSZ0 Size...
Page 290 ATmega48P/88P/168P/328P 24.8.15 ATmega168P Boot Loader Parameters Table 24-10 through Table 24-12, the parameters used in the description of the self programming are given. Table 24-10. Boot Size Configuration, ATmega168P Boot Application Loader Boot Flash Flash Application Boot Reset Address (Start Boot BOOTSZ1 BOOTSZ0 Size...
Page 291 ATmega48P/88P/168P/328P 24.8.16 ATmega328P Boot Loader Parameters Table 24-13 through Table 24-15, the parameters used in the description of the self programming are given. Table 24-13. Boot Size Configuration, ATmega328P Boot Application Loader Boot Flash Flash Application Boot Reset Address (Start Boot BOOTSZ1 BOOTSZ0 Size...
Page 292: Register Description
ATmega48P/88P/168P/328P 24.9 Register Description 24.9.1 SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to con- trol the Boot Loader operations. 0x37 (0x57) SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS...
Page 293 ATmega48P/88P/168P/328P PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. • Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes Page Erase.
Page 294: Memory Programming
ATmega48P/88P/168P/328P 25. Memory Programming 25.1 Program And Data Memory Lock Bits The ATmega88P/168P/328P provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 25-2. The Lock bits can only be erased to “1”...
Page 295: Fuse Bits
ATmega48P/88P/168P/328P (1)(2) Table 25-3. Lock Bit Protection Modes . Only ATmega88P/168P/328P. BLB0 Mode BLB02 BLB01 No restrictions for SPM or LPM accessing the Application section. SPM is not allowed to write to the Application section. SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
Page 296 ATmega48P/88P/168P/328P Table 25-5. Extended Fuse Byte for ATmega88P/168P Extended Fuse Byte Bit No Description Default Value – – – – – – – – – – Select Boot Size (see Table 24-7 on page 289, BOOTSZ1 0 (programmed) Table 24-10 on page 290 Table 24-13 on page 291 for details) Select Boot Size...
Page 297 ATmega48P/88P/168P/328P Table 25-7. Fuse High Byte for ATmega48P/88P/168P High Fuse Byte Bit No Description Default Value RSTDISBL External Reset Disable 1 (unprogrammed) DWEN debugWIRE Enable 1 (unprogrammed) Enable Serial Program and 0 (programmed, SPI SPIEN Data Downloading programming enabled) WDTON Watchdog Timer Always On 1 (unprogrammed) EEPROM memory is...
Page 298: Signature Bytes
25.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. For the ATmega48P/88P/168P/328P the signature...
Page 299: Calibration Byte
ATmega48P/88P/168P/328P 25.4 Calibration Byte The ATmega48P/88P/168P/328P has a byte calibration value for the Internal RC Oscillator. This byte resides in the high byte of address 0x000 in the signature address space. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the cali- brated RC Oscillator.
Page 300 ATmega48P/88P/168P/328P Figure 25-1. Parallel Programming +4.5 - 5.5V RDY/BSY +4.5 - 5.5V AVCC PC[1:0]:PB[5:0] DATA PAGEL +12 V RESET XTAL1 Note: - 0.3V < AV < V + 0.3V, however, AV should always be within 4.5 - 5.5V Table 25-13. Pin Name Mapping Signal Name in Programming Mode Pin Name...
Page 301: Parallel Programming
ATmega48P/88P/168P/328P Table 25-15. XA1 and XA0 Coding Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS1). Load Data (High or Low data byte for Flash determined by BS1). Load Command No Action, Idle Table 25-16.
Page 302 ATmega48P/88P/168P/328P 4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. 5. Wait until V actually reaches 4.5 -5.5V before giving any parallel programming commands. 6. Exit Programming mode by power the device down or by bringing RESET pin to 0V. 25.7.2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming.
Page 303 ATmega48P/88P/168P/328P 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. D.
Page 304 ATmega48P/88P/168P/328P Figure 25-2. Addressing the Flash Which is Organized in Pages PCMSB PAGEMSB PROGRAM PCPAGE PCWORD COUNTER PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE PROGRAM MEMORY PAGE PCWORD[PAGEMSB:0]: PAGE INSTRUCTION WORD PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 25-11 on page 299.
Page 305 ATmega48P/88P/168P/328P 5. E: Latch data (give PAGEL a positive pulse). K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page 1. Set BS1 to “0”. 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low.
Page 306 ATmega48P/88P/168P/328P 25.7.8 Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to ”Programming the Flash” on page 302 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3.
Page 307 ATmega48P/88P/168P/328P 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode.
Page 308: Serial Downloading
ATmega48P/88P/168P/328P 25.7.14 Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to ”Programming the Flash” on page 302 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte, 0x00. 3.
Page 309 ATmega48P/88P/168P/328P 25.8.1 Serial Programming Pin Mapping Table 25-17. Pin Mapping Serial Programming Symbol Pins Description MOSI Serial Data in MISO Serial Data out Serial Clock 25.8.2 Serial Programming Algorithm When writing serial data to the ATmega48P/88P/168P/328P, data is clocked on the rising edge of SCK.
Page 310 ATmega48P/88P/168P/328P not used, the used must wait at least t before issuing the next byte (See Table WD_EEPROM 25-18). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the con- tent at the selected address at serial output MISO.
Page 311 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers. If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’...
Page 312 ATmega48P/88P/168P/328P Figure 25-8. Serial Programming Instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Write Program Memory Page/ Load EEPROM Memory Page (page access) Write EEPROM Memory Page Byte 1 Byte 2 Byte 3 Byte 4 Byte 1 Byte 2 Byte 3 Byte 4...
Page 313: Electrical Characteristics
ATmega48P/88P/168P/328P 26. Electrical Characteristics 26.1 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Operating Temperature........-55°C to +125°C Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and Storage Temperature ........-65°C to +150°C functional operation of the device at these or Voltage on any Pin except RESET other conditions beyond those indicated in the...
Page 314 ATmega48P/88P/168P/328P = -40°C to 85°C, V = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min. Typ. Max. Units Reset Pull-up Resistor kΩ I/O Pin Pull-up Resistor kΩ = 5V Analog Comparator <10 ACIO Input Offset Voltage Analog Comparator = 5V ACLK Input Leakage Current...
Page 315 ATmega48P/88P/168P/328P 4. Maximum values are characterized values and not test limits in production. 26.2.2 ATmega88P DC Characteristics = -40°C to 85°C, V = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. Typ. Max. Units Active 1 MHz, V = 2V Active 4 MHz, V = 3V...
Page 316: Speed Grades
ATmega48P/88P/168P/328P 3. The current consumption values include input leakage current. 4. Maximum values are characterized values and not test limits in production. 26.2.4 ATmega328P DC Characteristics = -40°C to 85°C, V = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min.
Page 317 ATmega48P/88P/168P/328P Figure 26-1. Maximum Frequency vs. V , ATmega48P/88P/168PV 20 MHz 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V 4.5V 5.5V Figure 26-2. Maximum Frequency vs. V , ATmega48P/88P/168P 20 MHz 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V 4.5V 5.5V...
Page 318 ATmega48P/88P/168P/328P Figure 26-3. Maximum Frequency vs. V , ATmega328P 20 MHz 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V 4.5V 5.5V 8025I–AVR–02/09...
Page 319: Clock Characteristics
User 7.3 - 8.1 MHz -40°C - 85°C ±1% Calibration 2.7V - 5.5V Notes: 1. Voltage range for ATmega48PV/88PV/168PV/328PV. 2. Voltage range for ATmega48P/88P/168P/328P. 26.4.2 External Clock Drive Waveforms Figure 26-4. External Clock Drive Waveforms 26.4.3 External Clock Drive Table 26-2.
Page 320: System And Reset Characteristics
ATmega48P/88P/168P/328P 26.5 System and Reset Characteristics Table 26-3. Reset, Brown-out and Internal Voltage Characteristics Symbol Parameter Units Power-on Reset Threshold Voltage (rising) Power-on Reset Threshold Voltage (falling) Power-on Slope Rate 0.01 V/ms RESET Pin Threshold Voltage 0.2 V 0.9 V Minimum pulse width on RESET Pin µs Brown-out Detector Hysteresis...
Page 321: Spi Timing Characteristics
ATmega48P/88P/168P/328P 26.6 SPI Timing Characteristics Figure 26-5 Figure 26-6 for details. Table 26-5. SPI Timing Parameters Description Mode SCK period Master Table 16-5 SCK high/low Master 50% duty cycle Rise/Fall time Master Setup Master Hold Master Out to SCK Master 0.5 •...
Page 322 ATmega48P/88P/168P/328P Figure 26-5. SPI Interface Timing Requirements (Master Mode) (CPOL = 0) (CPOL = 1) MISO (Data Input) MOSI (Data Output) Figure 26-6. SPI Interface Timing Requirements (Slave Mode) (CPOL = 0) (CPOL = 1) MOSI (Data Input) MISO (Data Output) 8025I–AVR–02/09...
Page 323: Wire Serial Interface Characteristics
ATmega48P/88P/168P/328P 26.7 2-wire Serial Interface Characteristics Table 26-6 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega48P/88P/168P/328P 2- wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 26-7. Table 26-6.
Page 324 ATmega48P/88P/168P/328P 3. C = capacitance of one bus line in pF. 4. f = CPU clock frequency 5. This requirement applies to all ATmega48P/88P/168P/328P 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial Bus need only obey the general f requirement.
Page 325: Adc Characteristics - Preliminary Data
ATmega48P/88P/168P/328P 26.8 ADC Characteristics – Preliminary Data Table 26-7. ADC Characteristics Symbol Parameter Condition Units Resolution Bits = 4V, V = 4V, ADC clock = 200 kHz = 4V, V = 4V, ADC clock = 1 MHz Absolute accuracy (Including = 4V, V = 4V, INL, DNL, quantization error,...
Page 326: Parallel Programming Characteristics
ATmega48P/88P/168P/328P 26.9 Parallel Programming Characteristics Table 26-8. Parallel Programming Characteristics, V = 5V ± 10% Symbol Parameter Units Programming Enable Voltage 11.5 12.5 μA Programming Enable Current Data and Control Valid before XTAL1 High DVXH XTAL1 Low to XTAL1 High XLXH XTAL1 Pulse Width High XHXL...
Page 327 ATmega48P/88P/168P/328P Figure 26-8. Parallel Programming Timing, Including some General Timing Requirements XLWL XHXL XTAL1 DVXH XLDX Data & Contol (DATA, XA0/1, BS1, BS2) BVPH PLBX BVWL WLBX PAGEL PHPL WLWH PLWL WLRL RDY/BSY WLRH Figure 26-9. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD DATA LOAD ADDRESS LOAD DATA...
Page 328: Typical Characteristics
ATmega48P/88P/168P/328P 27. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave generator with rail-to-rail output is used as clock source.
Page 329: Atmega48P Typical Characteristics
ATmega48P/88P/168P/328P 27.1 ATmega48P Typical Characteristics 27.1.1 Active Supply Current Figure 27-1. Active Supply Current vs. Low Frequency (0.1-1.0 MHz). ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 0.1-1.0 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V Frequency (MHz) Figure 27-2.
Page 330 ATmega48P/88P/168P/328P Figure 27-3. Active Supply Current vs. V (Internal RC Oscillator, 128 kHz). ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 128 KHz 0.18 25 °C 0.16 85 °C -40 °C 0.14 0.12 0.08 0.06 0.04 0.02 Figure 27-4. Active Supply Current vs. V (Internal RC Oscillator, 1 MHz).
Page 331 ATmega48P/88P/168P/328P Figure 27-5. Active Supply Current vs. V (Internal RC Oscillator, 8 MHz). ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 85 °C 25 °C -40 °C 27.1.2 Idle Supply Current Figure 27-6. Idle Supply Current vs. Low Frequency (0.1-1.0 MHz). IDLE SUPPLY CURRENT vs.
Page 332 ATmega48P/88P/168P/328P Figure 27-7. Idle Supply Current vs. Frequency (1-20 MHz). IDLE SUPPLY CURRENT vs. FREQUENCY 1-20 MHz 5.5 V 5.0 V 4.5 V 4.0V 3.3V 2.7V 1.8V Frequency (MHz) Figure 27-8. Idle Supply Current vs. V (Internal RC Oscillator, 128 kHz). IDLE SUPPLY CURRENT vs.
Page 333 ATmega48P/88P/168P/328P Figure 27-9. Idle Supply Current vs. V (Internal RC Oscillator, 1 MHz). IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 85 °C 25 °C -40 °C Figure 27-10. Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz). IDLE SUPPLY CURRENT vs.
Page 334 ATmega48P/88P/168P/328P 27.1.3 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register”...
Page 335 ATmega48P/88P/168P/328P 27.1.4 Power-down Supply Current Figure 27-11. Power-Down Supply Current vs. V (Watchdog Timer Disabled). POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 85 °C 25 °C -40 °C Figure 27-12. Power-Down Supply Current vs. V (Watchdog Timer Enabled). POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED -40 °C 85 °C...
Page 336 ATmega48P/88P/168P/328P 27.1.5 Power-save Supply Current Figure 27-13. Power-Save Supply Current vs. V (Watchdog Timer Disabled and 32 kHz Crys- tal Oscillator Running). POWER-SAVE SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING 25 °C 27.1.6 Standby Supply Current Figure 27-14.
Page 337 ATmega48P/88P/168P/328P 27.1.7 Pin Pull-Up Figure 27-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 1.8 V). I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE = 1.8 V 85 °C 25 °C -40 °C Figure 27-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 2.7 V).
Page 338 ATmega48P/88P/168P/328P Figure 27-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 5 V). I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5 V 85 °C 25 °C -40 °C Figure 27-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 1.8 V).
Page 339 ATmega48P/88P/168P/328P Figure 27-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 2.7 V). RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE = 2.7 V 25 °C -40 °C 85 °C RESET Figure 27-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 5 V).
Page 340 ATmega48P/88P/168P/328P 27.1.8 Pin Driver Strength Figure 27-21. I/O Pin Output Voltage vs. Sink Current (V = 3 V). I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT = 3 V 85 °C 25 °C -40 °C (mA) Figure 27-22. I/O Pin Output Voltage vs. Sink Current (V = 5 V).
Page 341 ATmega48P/88P/168P/328P Figure 27-23. I/O Pin Output Voltage vs. Source Current (Vcc = 3 V). I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT = 3 V -40 °C 25 °C 85 °C (mA) Figure 27-24. I/O Pin Output Voltage vs. Source Current(V = 5 V).
Page 342 ATmega48P/88P/168P/328P 27.1.9 Pin Threshold and Hysteresis Figure 27-25. I/O Pin Input Threshold Voltage vs. V , I/O Pin read as ‘1’). I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' 85 °C 25 °C -40 °C Figure 27-26.
Page 343 ATmega48P/88P/168P/328P Figure 27-27. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 85 °C -40 °C 25 °C Figure 27-28. Reset Input Threshold Voltage vs. V , I/O Pin read as ‘1’). RESET INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' 85 °C 25 °C...
Page 344 ATmega48P/88P/168P/328P Figure 27-29. Reset Input Threshold Voltage vs. V , I/O Pin read as ‘0’). RESET INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' 85 °C 25 °C -40 °C Figure 27-30. Reset Pin Input Hysteresis vs. V RESET PIN INPUT HYSTERESIS vs.
Page 345 ATmega48P/88P/168P/328P 27.1.10 BOD Threshold Figure 27-31. BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V). BOD THRESHOLDS vs. TEMPERATURE Vcc = 1.8 V 1.88 1.86 1.84 Rising Vcc 1.82 Falling Vcc 1.78 1.76 1.74 1.72 Temperature (C) Figure 27-32. BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V). BOD THRESHOLDS vs.
Page 346 ATmega48P/88P/168P/328P Figure 27-33. BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V). BOD THRESHOLDS vs. TEMPERATURE Vcc = 4.3V 4.45 4.35 Rising Vcc 4.25 Falling Vcc Temperature (C) 27.1.11 Internal Oscilllator Speed Figure 27-34. Watchdog Oscillator Frequency vs. Temperature. WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 2.7 V 3.3 V 4.0 V...
Page 347 ATmega48P/88P/168P/328P Figure 27-35. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V -40 °C 25 °C 85 °C Figure 27-36. Calibrated 8 MHz RC Oscillator Frequency vs. V CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. V 85 °C 25 °C -40 °C 8025I–AVR–02/09...
Page 348 ATmega48P/88P/168P/328P Figure 27-37. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature. CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.15 5.0 V 3.0 V 8.05 7.95 7.85 Temperature Figure 27-38. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value. CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 85 °C 25 °C -40 °C...
Page 349 ATmega48P/88P/168P/328P 27.1.12 Current Consumption of Peripheral Units Figure 27-39. ADC Current vs. V (AREF = AV ADC CURRENT vs. V AREF = AV -40 °C 25 °C 85 °C Figure 27-40. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V -40 °C 25 °C 85 °C...
Page 350 ATmega48P/88P/168P/328P Figure 27-41. AREF External Reference Current vs. V AREF EXTERNAL REFERENCE CURRENT vs. V 85 °C 25 °C -40 °C Figure 27-42. Brownout Detector Current vs. V BROWNOUT DETECTOR CURRENT vs. V 85 °C 25 °C -40 °C 8025I–AVR–02/09...
Page 351 ATmega48P/88P/168P/328P Figure 27-43. Programming Current vs. V PROGRAMMING CURRENT vs. V -40 °C 25 °C 85 °C 27.1.13 Current Consumption in Reset and Reset Pulsewidth Figure 27-44. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz). RESET SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 0.25 5.5 V...
Page 352 ATmega48P/88P/168P/328P Figure 27-45. Reset Supply Current vs. Frequency (1 - 20 MHz). RESET SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 5.5 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V Frequency (MHz) Figure 27-46. Minimum Reset Pulse width vs. V MINIMUM RESET PULSE WIDTH vs.
Page 353: Atmega88P Typical Characteristics
ATmega48P/88P/168P/328P 27.2 ATmega88P Typical Characteristics 27.2.1 Active Supply Current Figure 27-47. Active Supply Current vs. Low Frequency (0.1-1.0 MHz). ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 5.5 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V Frequency (MHz) Figure 27-48.
Page 354 ATmega48P/88P/168P/328P Figure 27-49. Active Supply Current vs. V (Internal RC Oscillator, 128 kHz). ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 128 KHz 0.25 -40 °C 0.15 25 °C 85 °C 0.05 Figure 27-50. Active Supply Current vs. V (Internal RC Oscillator, 1 MHz). ACTIVE SUPPLY CURRENT vs.
Page 355 ATmega48P/88P/168P/328P Figure 27-51. Active Supply Current vs. V (Internal RC Oscillator, 8 MHz). ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 85 °C -40 °C 25 °C 27.2.2 Idle Supply Current Figure 27-52. Idle Supply Current vs. Low Frequency (0.1-1.0 MHz). IDLE SUPPLY CURRENT vs.
Page 356 ATmega48P/88P/168P/328P Figure 27-53. Idle Supply Current vs. Frequency (1-20 MHz). IDLE SUPPLY CURRENT vs. FREQUENCY 1-20 MHz 5.5 V 4.5 V 3.3 V 2.7 V 1.8 V Frequency (MHz) Figure 27-54. Idle Supply Current vs. V (Internal RC Oscillator, 128 kHz). IDLE SUPPLY CURRENT vs.
Page 357 ATmega48P/88P/168P/328P Figure 27-55. Idle Supply Current vs. V (Internal RC Oscillator, 1 MHz). IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz -40 °C 85 °C 25 °C Figure 27-56. Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz). IDLE SUPPLY CURRENT vs.
Page 358 ATmega48P/88P/168P/328P 27.2.3 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register”...
Page 359 ATmega48P/88P/168P/328P 27.2.4 Power-down Supply Current Figure 27-57. Power-Down Supply Current vs. V (Watchdog Timer Disabled). POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 85 °C 25 °C -40 °C Figure 27-58. Power-Down Supply Current vs. V (Watchdog Timer Enabled). POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 85 °C -40 °C...
Page 360 ATmega48P/88P/168P/328P 27.2.5 Power-save Supply Current Figure 27-59. Power-Save Supply Current vs. V (Watchdog Timer Disabled and 32 kHz Crys- tal Oscillator Running). P OW E R -S AV E S U P P LY C U R R ENT vs. V WATC HD OG TIM ER D ISAB LED a n d 32 kH z C RYS TA L OSC IL L ATO R RUN NI NG 1.
Page 361 ATmega48P/88P/168P/328P 27.2.7 Pin Pull-Up Figure 27-61. I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 1.8 V). I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE = 1.8 V 25 °C -40 °C 85 °C Figure 27-62. I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 2.7 V).
Page 362 ATmega48P/88P/168P/328P Figure 27-63. I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 5 V). I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE = 5 V 25 °C -40 °C 85 °C Figure 27-64. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 1.8 V).
Page 363 ATmega48P/88P/168P/328P Figure 27-65. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 2.7 V). RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE = 2.7 V 25 °C -40 °C 85 °C RESET Figure 27-66. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 5 V).
Page 364 ATmega48P/88P/168P/328P 27.2.8 Pin Driver Strength Figure 27-67. I/O Pin Output Voltage vs. Sink Current(V = 3 V). I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT = 3 V 85 °C 25 °C -40 °C (mA) Figure 27-68. I/O Pin Output Voltage vs. Sink Current(V = 5 V).
Page 365 ATmega48P/88P/168P/328P Figure 27-69. I/O Pin Output Voltage vs. Source Current(Vcc = 3 V). I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT = 3 V -40 °C 25 °C 85 °C (mA) Figure 27-70. I/O Pin Output Voltage vs. Source Current(V = 5 V). I/O PIN OUTPUT VOLTAGE vs.
Page 366 ATmega48P/88P/168P/328P 27.2.9 Pin Threshold and Hysteresis Figure 27-71. I/O Pin Input Threshold Voltage vs. V , I/O Pin read as ‘1’). I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' -40 °C 25 °C 85 °C Figure 27-72.
Page 367 ATmega48P/88P/168P/328P Figure 27-73. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V -40 °C 25 °C 85 °C Figure 27-74. Reset Input Threshold Voltage vs. V , I/O Pin read as ‘1’). RESET INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' -40 °C 25 °C...
Page 368 ATmega48P/88P/168P/328P Figure 27-75. Reset Input Threshold Voltage vs. V , I/O Pin read as ‘0’). RESET INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' 85 °C 25 °C -40 °C Figure 27-76. Reset Pin Input Hysteresis vs. V RESET PIN INPUT HYSTERESIS vs.
Page 369 ATmega48P/88P/168P/328P 27.2.10 BOD Threshold Figure 27-77. BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V). BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 1.8 V Rising Vcc Falling Vcc Temperature (C) Figure 27-78. BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V). BOD THRESHOLDS vs. TEMPERATURE 2.95 2.85 Rising Vcc...
Page 370 ATmega48P/88P/168P/328P Figure 27-79. BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V). BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.3 V 4.45 4.35 Rising Vcc 4.25 Falling Vcc 4.15 4.05 Temperature (C) 27.2.11 Internal Oscilllator Speed Figure 27-80. Watchdog Oscillator Frequency vs. Temperature. WATCHDOG OSCILLATOR FREQUENCY vs.
Page 371 ATmega48P/88P/168P/328P Figure 27-81. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V -40 °C 25 °C 85 °C Figure 27-82. Calibrated 8 MHz RC Oscillator Frequency vs. V CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. V 85 °C 25 °C -40 °C 8025I–AVR–02/09...
Page 372 ATmega48P/88P/168P/328P Figure 27-83. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature. CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.0 V 3.0 V Temperature Figure 27-84. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value. CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 85 °C 25 °C -40 °C...
Page 373 ATmega48P/88P/168P/328P 27.2.12 Current Consumption of Peripheral Units Figure 27-85. ADC Current vs. V (AREF = AV ADC CURRENT vs. Vcc AREF = AV -40 °C 25 °C Figure 27-86. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V -40 °C 85 °C 25 °C 8025I–AVR–02/09...
Page 374 ATmega48P/88P/168P/328P Figure 27-87. AREF External Reference Current vs. V AREF EXTERNAL REFERENCE CURRENT vs. V 85 °C 25 °C -40 °C Figure 27-88. Brownout Detector Current vs. V BROWNOUT DETECTOR CURRENT vs. V -40 °C 25 °C 85 °C 8025I–AVR–02/09...
Page 375 ATmega48P/88P/168P/328P Figure 27-89. Programming Current vs. V PROGRAMMING CURRENT vs. V -40 °C 25 °C 85 °C 27.2.13 Current Consumption in Reset and Reset Pulsewidth Figure 27-90. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz). RESET SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 0.25 5.5 V...
Page 376 ATmega48P/88P/168P/328P Figure 27-91. Reset Supply Current vs. Frequency (1 - 20 MHz). RESET SUPPLY CURRENT vs. FREQUENCY 1-20 MHz 5.5 V 4.5 V 3.3 V 2.7 V 1.8 V Frequency (MHz) Figure 27-92. Minimum Reset Pulse width vs. V MINIMUM RESET PULSE WIDTH vs. V 2000 1800 1600...
Page 377: Atmega168P Typical Characteristics
ATmega48P/88P/168P/328P 27.3 ATmega168P Typical Characteristics 27.3.1 Active Supply Current Figure 27-93. Active Supply Current vs. Low Frequency (0.1-1.0 MHz). ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 5.5 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V Frequency (MHz) Figure 27-94.
Page 378 ATmega48P/88P/168P/328P Figure 27-95. Active Supply Current vs. V (Internal RC Oscillator, 128 kHz). ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 128 KHz 0.18 85 °C 0.16 25 °C -40 °C 0.14 0.12 0.08 0.06 0.04 0.02 Figure 27-96. Active Supply Current vs. V (Internal RC Oscillator, 1 MHz).
Page 379 ATmega48P/88P/168P/328P Figure 27-97. Active Supply Current vs. V (Internal RC Oscillator, 8 MHz). ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 85 °C 25 °C -40 °C 27.3.2 Idle Supply Current Figure 27-98. Idle Supply Current vs. Low Frequency (0.1-1.0 MHz). IDLE SUPPLY CURRENT vs.
Page 380 ATmega48P/88P/168P/328P Figure 27-99. Idle Supply Current vs. Frequency (1-20 MHz). IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V Frequency (MHz) Figure 27-100.Idle Supply Current vs. V (Internal RC Oscillator, 128 kHz).
Page 381 ATmega48P/88P/168P/328P Figure 27-101.Idle Supply Current vs. V (Internal RC Oscillator, 1 MHz). IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 85 °C 0.45 25 °C -40 °C 0.35 0.25 0.15 0.05 Figure 27-102.Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz). IDLE SUPPLY CURRENT vs.
Page 382 ATmega48P/88P/168P/328P 27.3.3 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register”...
Page 383 ATmega48P/88P/168P/328P 27.3.4 Power-down Supply Current Figure 27-103.Power-Down Supply Current vs. V (Watchdog Timer Disabled). POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 85 °C 25 °C -40 °C Figure 27-104.Power-Down Supply Current vs. V (Watchdog Timer Enabled). POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 85 °C -40 °C...
Page 384 ATmega48P/88P/168P/328P 27.3.5 Power-save Supply Current Figure 27-105.Power-Save Supply Current vs. V (Watchdog Timer Disabled and 32 kHz Crystal Oscillator Running). POWER-SAVE SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING 25 °C 27.3.6 Standby Supply Current Figure 27-106.Standby Supply Current vs.
Page 385 ATmega48P/88P/168P/328P 27.3.7 Pin Pull-Up Figure 27-107.I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 1.8 V). I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE = 1.8V 25 °C -40 °C 85 °C Figure 27-108.I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 2.7 V).
Page 386 ATmega48P/88P/168P/328P Figure 27-109.I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 5 V). I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE = 5V 25 °C -40 °C 85 °C Figure 27-110.Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 1.8 V).
Page 387 ATmega48P/88P/168P/328P Figure 27-111.Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 2.7 V). RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE = 2.7V 25 °C -40 °C 85 °C RESET Figure 27-112.Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 5 V).
Page 388 ATmega48P/88P/168P/328P 27.3.8 Pin Driver Strength Figure 27-113.I/O Pin Output Voltage vs. Sink Current(V = 3 V). I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT = 3V 85 °C 25 °C -40 °C (mA) Figure 27-114.I/O Pin Output Voltage vs. Sink Current(V = 5 V).
Page 389 ATmega48P/88P/168P/328P Figure 27-115.I/O Pin Output Voltage vs. Source Current(Vcc = 3 V). I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT = 3V, NORMAL POWER PINS -40 °C 25 °C 85 °C (mA) Figure 27-116.I/O Pin Output Voltage vs. Source Current(V = 5 V). I/O PIN OUTPUT VOLTAGE vs.
Page 390 ATmega48P/88P/168P/328P 27.3.9 Pin Threshold and Hysteresis Figure 27-117.I/O Pin Input Threshold Voltage vs. V , I/O Pin read as ‘1’). I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' 85 °C 25 °C -40 °C Figure 27-118.I/O Pin Input Threshold Voltage vs. V , I/O Pin read as ‘0’).
Page 391 ATmega48P/88P/168P/328P Figure 27-119.I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 85 °C 25 °C -40 °C Figure 27-120.Reset Input Threshold Voltage vs. V , I/O Pin read as ‘1’). RESET INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' 85 °C 25 °C -40 °C...
Page 392 ATmega48P/88P/168P/328P Figure 27-121.Reset Input Threshold Voltage vs. V , I/O Pin read as ‘0’). RESET INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' -40 °C 85 °C 25 °C Figure 27-122.Reset Pin Input Hysteresis vs. V RESET PIN INPUT HYSTERESIS vs. V -4 0°C 2 5°C 8 5°C...
Page 393 ATmega48P/88P/168P/328P 27.3.10 BOD Threshold Figure 27-123.BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V). BOD THRESHOLDS vs. TEMPERATURE Vcc =1.8V 1.88 1.86 1.84 Rising Vcc 1.82 Falling Vcc 1.78 1.76 1.74 1.72 Temperature (C) Figure 27-124.BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V). BOD THRESHOLDS vs.
Page 394 ATmega48P/88P/168P/328P Figure 27-125.BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V). BOD THRESHOLDS vs. TEMPERATURE Vcc = 4.3V 4.45 4.35 Rising Vcc 4.25 Falling Vcc 4.15 4.05 Temperature (C) 27.3.11 Internal Oscilllator Speed Figure 27-126.Watchdog Oscillator Frequency vs. Temperature. WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 2.7 V 3.3 V 5.0 V...
Page 395 ATmega48P/88P/168P/328P Figure 27-127.Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 25 °C 85 °C Figure 27-128.Calibrated 8 MHz RC Oscillator Frequency vs. V CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 85 °C 8.05 25 °C 7.95 7.85 8025I–AVR–02/09...
Page 396 ATmega48P/88P/168P/328P Figure 27-129.Calibrated 8 MHz RC Oscillator Frequency vs. Temperature. CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.15 5.5 V 8.05 2.7 V 7.95 7.85 1.8 V Temperature Figure 27-130.Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value. CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 25 °C 85 °C OSCCAL (X1)
Page 397 ATmega48P/88P/168P/328P 27.3.12 Current Consumption of Peripheral Units Figure 27-131.ADC Current vs. V (AREF = AV ADC CURRENT vs. V AREF = AV 25 °C 85 °C -40 °C Figure 27-132.Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V -40 °C 25 °C 85 °C 8025I–AVR–02/09...
Page 398 ATmega48P/88P/168P/328P Figure 27-133.AREF External Reference Current vs. V AREF CURRENT EXTERNAL REFERENCE CURRENT vs. V 25 °C 85 °C -40 °C Figure 27-134.Brownout Detector Current vs. V BROWNOUT DETECTOR CURRENT vs. V 25 °C 85 °C -40 °C 8025I–AVR–02/09...
Page 399 ATmega48P/88P/168P/328P Figure 27-135.Programming Current vs. V PROGRAMMING CURRENT vs. Vcc -40 °C 85 °C 25 °C 27.3.13 Current Consumption in Reset and Reset Pulsewidth Figure 27-136.Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz). RESET SUPPLY CURRENT vs. V 0.1 - 1.0 MHz 5.5 V 0.18...
Page 400 ATmega48P/88P/168P/328P Figure 27-137.Reset Supply Current vs. Frequency (1 - 20 MHz). RESET SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V Frequency (MHz) Figure 27-138.Minimum Reset Pulse width vs. V MINIMUM RESET PULSE WIDTH vs.
Page 401: Atmega328P Typical Characteristics
ATmega48P/88P/168P/328P 27.4 ATmega328P Typical Characteristics 27.4.1 Active Supply Current Figure 27-139.Active Supply Current vs. Low Frequency (0.1-1.0 MHz). ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V Frequency (MHz) Figure 27-140.Active Supply Current vs.
Page 402 ATmega48P/88P/168P/328P Figure 27-141.Active Supply Current vs. V (Internal RC Oscillator, 128 kHz). ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 128 kHz 0.16 85 °C 25 °C -40 °C 0.12 0.08 0.04 Figure 27-142.Active Supply Current vs. V (Internal RC Oscillator, 1 MHz). ACTIVE SUPPLY CURRENT vs.
Page 403 ATmega48P/88P/168P/328P Figure 27-143.Active Supply Current vs. V (Internal RC Oscillator, 8 MHz). ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 85 °C 25 °C -40 °C 27.4.2 Idle Supply Current Figure 27-144.Idle Supply Current vs. Low Frequency (0.1-1.0 MHz). IDLE SUPPLY CURRENT vs.
Page 404 ATmega48P/88P/168P/328P Figure 27-145.Idle Supply Current vs. Frequency (1-20 MHz). IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V Frequency (MHz) Figure 27-146.Idle Supply Current vs. V (Internal RC Oscillator, 128 kHz).
Page 405 ATmega48P/88P/168P/328P Figure 27-147.Idle Supply Current vs. V (Internal RC Oscillator, 1 MHz). IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 85 °C 0.35 25 °C -40 °C 0.25 0.15 0.05 Figure 27-148.Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz). IDLE SUPPLY CURRENT vs.
Page 406 ATmega48P/88P/168P/328P 27.4.3 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”Power Reduction Register”...
Page 407 ATmega48P/88P/168P/328P 27.4.4 Power-down Supply Current Figure 27-149.Power-Down Supply Current vs. V (Watchdog Timer Disabled). POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 85 °C 25 °C -40 °C Figure 27-150.Power-Down Supply Current vs. V (Watchdog Timer Enabled). POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED -40 °C 85 °C...
Page 408 ATmega48P/88P/168P/328P 27.4.5 Power-save Supply Current Figure 27-151.Power-Save Supply Current vs. V (Watchdog Timer Disabled and 32 kHz Crystal Oscillator Running). POWER-SAVE SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING 25 °C 27.4.6 Standby Supply Current Figure 27-152.Standby Supply Current vs.
Page 409 ATmega48P/88P/168P/328P 27.4.7 Pin Pull-Up Figure 27-153.I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 1.8 V). I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE = 1.8V 25 °C 85 °C -40 °C Figure 27-154.I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 2.7 V).
Page 410 ATmega48P/88P/168P/328P Figure 27-155.I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 5 V). I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE = 5V 25 °C 85 °C -40 °C Figure 27-156.Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 1.8 V).
Page 411 ATmega48P/88P/168P/328P Figure 27-157.Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 2.7 V). RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE = 2.7V 25 °C 85 °C -40 °C RESET Figure 27-158.Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 5 V).
Page 412 ATmega48P/88P/168P/328P 27.4.8 Pin Driver Strength Figure 27-159.I/O Pin Output Voltage vs. Sink Current(V = 3 V). I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT = 3V 85 °C 25 °C -40 °C (mA) Figure 27-160.I/O Pin Output Voltage vs. Sink Current(V = 5 V).
Page 413 ATmega48P/88P/168P/328P Figure 27-161.I/O Pin Output Voltage vs. Source Current(Vcc = 3 V). I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT = 3V -40 °C 25 °C 85 °C (mA) Figure 27-162.I/O Pin Output Voltage vs. Source Current(V = 5 V). I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT = 5V -40 °C 25 °C...
Page 414 ATmega48P/88P/168P/328P 27.4.9 Pin Threshold and Hysteresis Figure 27-163.I/O Pin Input Threshold Voltage vs. V , I/O Pin read as ‘1’). I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' -40 °C 25 °C 85 °C Figure 27-164.I/O Pin Input Threshold Voltage vs. V , I/O Pin read as ‘0’).
Page 415 ATmega48P/88P/168P/328P Figure 27-165.I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V -40 °C 25 °C 85 °C Figure 27-166.Reset Input Threshold Voltage vs. V , I/O Pin read as ‘1’). RESET INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' -40 °C 25 °C 85 °C...
Page 416 ATmega48P/88P/168P/328P Figure 27-167.Reset Input Threshold Voltage vs. V , I/O Pin read as ‘0’). RESET INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' 85 °C 25 °C -40 °C Figure 27-168.Reset Pin Input Hysteresis vs. V RESET PIN INPUT HYSTERESIS vs. V -40 °C 25 °C 85 °C...
Page 417 ATmega48P/88P/168P/328P 27.4.10 BOD Threshold Figure 27-169.BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V). BOD THRESHOLDS vs. TEMPERATURE = 1.8V 1.85 1.83 1.81 1.79 1.77 1.75 Temperature (C) Figure 27-170.BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V). BOD THRESHOLDS vs. TEMPERATURE = 2.7V 2.78 2.76...
Page 418 ATmega48P/88P/168P/328P Figure 27-171.BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V). BOD THRESHOLDS vs. TEMPERATURE = 4.3V 4.35 4.25 Temperature (C) 27.4.11 Internal Oscilllator Speed Figure 27-172.Watchdog Oscillator Frequency vs. Temperature. WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 2.7 V 3.3 V 4.0 V 5.5 V Temperature 8025I–AVR–02/09...
Page 419 ATmega48P/88P/168P/328P Figure 27-173.Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V -40 °C 25 °C 85 °C Figure 27-174.Calibrated 8 MHz RC Oscillator Frequency vs. V CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. V 85 °C 25 °C -40 °C CC (V) 8025I–AVR–02/09...
Page 420 ATmega48P/88P/168P/328P Figure 27-175.Calibrated 8 MHz RC Oscillator Frequency vs. Temperature. CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.0 V 3.0 V Temperature Figure 27-176.Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value. CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 85 °C 25 °C -40 °C...
Page 421 ATmega48P/88P/168P/328P 27.4.12 Current Consumption of Peripheral Units Figure 27-177.ADC Current vs. V (AREF = AV ADC CURRENT vs. V AREF = AV -40 °C 25 °C 85 °C Figure 27-178.Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V -40 °C 25 °C 85 °C 8025I–AVR–02/09...
Page 422 ATmega48P/88P/168P/328P Figure 27-179.AREF External Reference Current vs. V AREF EXTERNAL REFERENCE CURRENT vs. V 85 °C 25 °C -40 °C Figure 27-180.Brownout Detector Current vs. V BROWNOUT DETECTOR CURRENT vs. V 85 °C 25 °C -40 °C 8025I–AVR–02/09...
Page 423 ATmega48P/88P/168P/328P Figure 27-181.Programming Current vs. V PROGRAMMING CURRENT vs. V 25 °C 85 °C -40 °C 27.4.13 Current Consumption in Reset and Reset Pulsewidth Figure 27-182.Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz). RESET SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 0.15 5.5 V...
Page 424 ATmega48P/88P/168P/328P Figure 27-183.Reset Supply Current vs. Frequency (1 - 20 MHz). RESET SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V Frequency (MHz) Figure 27-184.Minimum Reset Pulse width vs. V MINIMUM RESET PULSE WIDTH vs.
Page 425: Register Summary
ATmega48P/88P/168P/328P 28. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xFF) Reserved – – – – – – – – (0xFE) Reserved – – – – – –...
Page 426 ATmega48P/88P/168P/328P Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 (0xC0) UCSR0A RXC0 TXC0 UDRE0 DOR0 UPE0 U2X0 MPCM0 (0xBF) Reserved –...
Page 427 ATmega48P/88P/168P/328P Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7F) DIDR1 – – – – – – AIN1D AIN0D (0x7E) DIDR0 – – ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D (0x7D) Reserved –...
Page 428 ATmega48P/88P/168P/328P Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1D (0x3D) EIMSK – – – – – – INT1 INT0 0x1C (0x3C) EIFR – – – – – – INTF1 INTF0 0x1B (0x3B)
Page 429: Instruction Set Summary
ATmega48P/88P/168P/328P 29. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS Rd ← Rd + Rr Rd, Rr Add two Registers Z,C,N,V,H Rd ← Rd + Rr + C Rd, Rr Add with Carry two Registers Z,C,N,V,H Rdh:Rdl ←...
Page 430 ATmega48P/88P/168P/328P Mnemonics Operands Description Operation Flags #Clocks if ( I = 1) then PC ← PC + k + 1 BRIE Branch if Interrupt Enabled None if ( I = 0) then PC ← PC + k + 1 BRID Branch if Interrupt Disabled None BIT AND BIT-TEST INSTRUCTIONS...
Page 431 ATmega48P/88P/168P/328P Mnemonics Operands Description Operation Flags #Clocks Rd ← STACK Pop Register from Stack None MCU CONTROL INSTRUCTIONS No Operation None SLEEP Sleep (see specific descr. for Sleep function) None Watchdog Reset (see specific descr. for WDR/timer) None BREAK Break For On-chip Debug Only None Note:...
Page 432: Ordering Information
28P3 Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green.
Page 433: Atmega88P
28P3 Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green.
Page 434: Atmega168P
28P3 Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green.
Page 435: Atmega328P
28P3 Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green.
Page 436: Packaging Information
ATmega48P/88P/168P/328P 31. Packaging Information 31.1 PIN 1 PIN 1 IDENTIFIER 0˚~7˚ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL NOTE – – 1.20 0.05 – 0.15 0.95 1.00 1.05 8.75 9.00 9.25 6.90 7.00 7.10 Note 2 8.75 9.00 9.25 Notes: 1.
Page 437 TITLE DRAWING NO. REV. 28M1, 28-pad, 4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm, Package Drawing Contact: 28M1 2.4 x 2.4 mm Exposed Pad, Thermally Enhanced packagedrawings@atmel.com Plastic Very Thin Quad Flat No Lead Package (VQFN) 8025I–AVR–02/09...
Page 438: M1-A
ATmega48P/88P/168P/328P 31.3 32M1-A Pin 1 ID SIDE VIEW TOP VIEW COMMON DIMENSIONS 0.08 C (Unit of Measure = mm) NOTE SYMBOL 0.80 0.90 1.00 – 0.02 0.05 – 0.65 1.00 Pin #1 Notch (0.20 R) 0.20 REF 0.18 0.23 0.30 4.90 5.00 5.10...
Page 439 ATmega48P/88P/168P/328P 31.4 28P3 SEATING PLANE (4 PLACES) COMMON DIMENSIONS (Unit of Measure = mm) 0º ~ 15º SYMBOL NOTE – – 4.5724 0.508 – – 34.544 – 34.798 Note 1 7.620 – 8.255 7.112 – 7.493 Note 1 0.381 – 0.533 1.143 –...
Page 440: Errata
ATmega48P/88P/168P/328P 32. Errata 32.1 Errata ATmega48P The revision letter in this section refers to the revision of the ATmega48P device. 32.1.1 Rev. C No known errata. 32.1.2 Rev. B No known errata. 32.1.3 Rev. A Not Sampled. 32.2 Errata ATmega88P The revision letter in this section refers to the revision of the ATmega88P device.
Page 441 ATmega48P/88P/168P/328P Problem Fix/ Workaround None 32.4.3 Rev A • Unstable 32 kHz Oscillator 1. Unstable 32 kHz Oscillator The 32 kHz oscillator does not work as system clock. The 32 kHz oscillator used as asynchronous timer is inaccurate. Problem Fix/ Workaround None 8025I–AVR–02/09...
Page 442: Datasheet Revision History
ATmega48P/88P/168P/328P 33. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 33.1 Rev. 2545I-02/09 Removed “preliminary” from ATmega48P/88P/168P. 33.2 Rev.
Page 443: Rev. 2545F-08/08
ATmega48P/88P/168P/328P 33.4 Rev. 2545F-08/08 Updated ”ATmega328P Typical Characteristics” on page 401 with Power-save numbers. Added ATmega328P ”Standby Supply Current” on page 408. 33.5 Rev. 2545E-08/08 Updated description of ”Stack Pointer” on page Updated description of use of external capacitors in ”Low Frequency Crystal Oscilla- tor”...
Page 444: Rev. 2545B-01/08
ATmega48P/88P/168P/328P 33.8 Rev. 2545B-01/08 Updated ”Features” on page Added ”Data Retention” on page Updated Table 6-2 on page Removed “Low-frequency Crystal Oscillator Internal Load Capacitance“ table from”Low Frequency Crystal Oscillator” on page Removed JTD bit from ”MCUCR – MCU Control Register” on page Updated typical and general program setup for Reset and Interrupt Vector Addresses ”Interrupt Vectors in ATmega168P”...
Page 445: Table Of Contents
ATmega48P/88P/168P/328P Table of Contents Features ..................... 1 Pin Configurations ................... 2 1.1Pin Descriptions ......................3 Overview ....................4 2.1Block Diagram ......................5 2.2Comparison Between ATmega48P, ATmega88P, ATmega168P, and ATmega328P 6 About ......................7 3.1Disclaimer ........................7 3.2Resources .........................7 3.3Data Retention ......................7 3.4Code Examples ......................7 AVR CPU Core ..................
Page 446 ATmega48P/88P/168P/328P 6.6Calibrated Internal RC Oscillator ................33 6.7128 kHz Internal Oscillator ..................33 6.8External Clock ......................34 6.9Clock Output Buffer ....................35 6.10Timer/Counter Oscillator ..................35 6.11System Clock Prescaler ..................35 6.12Register Description ....................37 Power Management and Sleep Modes ..........39 7.1Sleep Modes ......................39 7.2BOD Disable ......................40 7.3Idle Mode .........................40 7.4ADC Noise Reduction Mode ..................40 7.5Power-down Mode ....................41...
Page 447 ATmega48P/88P/168P/328P 10 External Interrupts ................. 70 10.1Pin Change Interrupt Timing ..................70 10.2Register Description ....................71 11 I/O-Ports ....................75 11.1Overview ........................75 11.2Ports as General Digital I/O ...................76 11.3Alternate Port Functions ..................80 11.4Register Description ....................92 12 8-bit Timer/Counter0 with PWM ............94 12.1Features ........................94 12.2Overview ........................94 12.3Timer/Counter Clock Sources ................96...
Page 448 ATmega48P/88P/168P/328P 15 8-bit Timer/Counter2 with PWM and Asynchronous Operation ..144 15.1Features ......................144 15.2Overview ......................144 15.3Timer/Counter Clock Sources ................145 15.4Counter Unit ......................145 15.5Output Compare Unit ...................146 15.6Compare Match Output Unit ................148 15.7Modes of Operation .....................149 15.8Timer/Counter Timing Diagrams .................153 15.9Asynchronous Operation of Timer/Counter2 ............155 15.10Timer/Counter Prescaler ...................156 15.11Register Description ..................158 16 SPI –...
Page 449 ATmega48P/88P/168P/328P 18.5Frame Formats ....................206 18.6Data Transfer .......................208 18.7AVR USART MSPIM vs. AVR SPI ..............210 18.8Register Description ....................211 19 2-wire Serial Interface ................214 19.1Features ......................214 19.22-wire Serial Interface Bus Definition ..............214 19.3Data Transfer and Frame Format ................216 19.4Multi-master Bus Systems, Arbitration and Synchronization .......218 19.5Overview of the TWI Module ................221 19.6Using the TWI ......................223 19.7Transmission Modes ...................227...
Page 450 ATmega48P/88P/168P/328P 23 Self-Programming the Flash, ATmega48P ......... 269 23.1Overview ......................269 23.2Addressing the Flash During Self-Programming ..........270 23.3Register Description’ ...................275 24 Boot Loader Support – Read-While-Write Self-Programming, ATmega88P, ATmega168P and ATmega328P 277 24.1Features ......................277 24.2Overview ......................277 24.3Application and Boot Loader Flash Sections ............277 24.4Read-While-Write and No Read-While-Write Flash Sections ......278 24.5Boot Loader Lock Bits ..................280 24.6Entering the Boot Loader Program ..............281...
Page 451 ATmega48P/88P/168P/328P 27.1ATmega48P Typical Characteristics ..............329 27.2ATmega88P Typical Characteristics ..............353 27.3ATmega168P Typical Characteristics ..............377 27.4ATmega328P Typical Characteristics ..............401 28 Register Summary ................425 29 Instruction Set Summary ..............429 30 Ordering Information ................432 30.1ATmega48P ......................432 30.2ATmega88P ......................433 30.3ATmega168P .......................434 30.4ATmega328P .......................435 31 Packaging Information ................
Page 452 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

This manual is also suitable for:

Atmega88pv Tmega48p Atmega88p Atmega168p Atmega328p Atmega168pv ... Show all

Atmel ATmega48PV Manual

Features

1 Pin Configurations

2 Overview

3 About

4 AVR CPU Core

5 AVR Memories

6 System Clock and Clock Options

7 Power Management and Sleep Modes

8 System Control and Reset

9 Interrupts

10 External Interrupts

11 O-Ports

12 8-Bit Timer/Counter0 with PWM

16 Bit Timer/Counter1 with PWM

14 Timer/Counter0 and Timer/Counter1 Prescalers

15 8-Bit Timer/Counter2 with PWM and Asynchronous Operation

16 SPI - Serial Peripheral Interface

17 Usart0

18 USART in SPI Mode

19 2-Wire Serial Interface

20 Analog Comparator

21 Analog-To-Digital Converter

22 Debugwire On-Chip Debug System

23 Self-Programming the Flash, Atmega48P

24 Boot Loader Support - Read-While-Write Self-Programming, Atmega88P, Atmega168P and Atmega328P

25 Memory Programming

26 Electrical Characteristics

27 Typical Characteristics

28 Register Summary

29 Instruction Set Summary

30 Ordering Information

31 Packaging Information

32 Errata

33 Datasheet Revision History

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Features

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Summary of Contents for Atmel ATmega48PV