Page 1 – 2.7V - 5.5V for the ATmega161L – 4.0V - 5.5V for the ATmega161 • Speed Grades – 0 - 4 MHz for the ATmega161L – 0 - 8 MHz for the ATmega161 • Commercial and Industrial Temperature Ranges Rev. 1228B–09/01...
Page 2: Pin Configuration
PA7 (AD7) RESET (RXD0) PD0 PE0 (ICP/INT2) (TXD0) PD1 PE1 (ALE) (INT0) PD2 PE2 (OC1B) (INT1) PD3 PC7 (A15) (TOSC1) PD4 PC6 (A14) (OCIA/TOSC2) PD5 PC5 (A13) * NC = Do not connect (Can be used in future devices) ATmega161(L) 1228B–09/01...
Page 3 The ATmega161 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits.
Page 4: Block Diagram
Block Diagram Figure 1. The ATmega161 Block Diagram PC0-PC7 PA0-PA7 PORTA DRIVERS PORTC DRIVERS DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. PORTA REG. PORTA PORTC REG. PORTC 8-BIT DATA BUS XTAL1 INTERNAL OSCILLATOR OSCILLATOR XTAL2 PROGRAM STACK TIMING AND...
Page 5: Pin Descriptions
The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega161 as listed on page 90.
Page 6: Crystal Oscillator
To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3. Figure 2. Oscillator Connections XTAL2 XTAL1 Figure 3. External Clock Drive Configuration XTAL2 EXTERNAL XTAL1 OSCILLATOR SIGNAL ATmega161(L) 1228B–09/01...
Page 7: Architectural Overview
The ALU supports arithmetic and logic functions between registers or between a con- stant and a register. Single register operations are also executed in the ALU. Figure 4 shows the ATmega161 AVR RISC microcontroller architecture. Figure 4. The ATmega161 AVR RISC Architecture...
Page 8 I/O space. The 1K byte data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. ATmega161(L) 1228B–09/01...
Page 9 ATmega161(L) Figure 5. Memory Maps Data Memory Program Memory $0000 $000 32 Gen. Purpose Working Registers $001F $0020 64 I/O Registers Program Flash (8K x 16) $005F $0060 Internal SRAM (1024 x 8) $045F $0460 External SRAM (0 - 63K x 8)
Page 10: The General Purpose Register File
These registers are address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as: Figure 7. X-, Y-, and Z-registers X-register R27 ($1B) R26 ($1A) Y-register R29 ($1D) R28 ($1C) Z-register R31 ($1F) R30 ($1E) ATmega161(L) 1228B–09/01...
Page 11: Alu - Arithmetic Logic Unit
See page 13 for the different program memory addressing modes. EEPROM Data Memory The ATmega161 contains 512 bytes of data EEPROM memory. It is organized as a sep- arate data space in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles per location.
Page 12: Sram Data Memory
SRAM Data Memory Figure 8 shows how the ATmega161 SRAM memory is organized. Figure 8. SRAM Organization Register File Data Address Space $0000 $0001 $0002 … … $001D $001E $001F I/O Registers $0020 $0021 $0022 … … $005D $005E $005F...
Page 13: Program And Data Addressing Modes
The 32 general purpose working registers, 64 I/O registers and the 1K byte of internal data SRAM in the ATmega161 are all accessible through all these addressing modes. See the next section for a detailed description of the different addressing modes.
Page 14 Data Direct Figure 12. Direct Data Addressing Data Space $0000 20 19 Rr/Rd 16 LSBs $FFFF A 16-bit data address is contained in the 16 LSBs of a two-word instruction. Rd/Rr spec- ify the destination or source register. ATmega161(L) 1228B–09/01...
Page 15 ATmega161(L) Data Indirect with Figure 13. Data Indirect with Displacement Displacement Data Space $0000 Y OR Z - REGISTER $FFFF Operand address is the result of the Y- or Z-register contents added to the address con- tained in six bits of the instruction word.
Page 16 (0 - 8K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). Indirect Program Addressing, Figure 18. Indirect Program Memory Addressing IJMP and ICALL PROGRAM MEMORY $000 Z-REGISTER $1FFF ATmega161(L) 1228B–09/01...
Page 17 ATmega161(L) Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). Relative Program Addressing, Figure 19. Relative Program Memory Addressing RJMP and RCALL PROGRAM MEMORY $000 12 11 $1FFF Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.
Page 18 ALU Operation Execute Result Write Back The internal data SRAM access is performed in two System Clock cycles as described in Figure 23. Figure 23. On-chip Data SRAM Access Cycles System Clock Ø Address Prev. Address Address Data Data ATmega161(L) 1228B–09/01...
Page 19 ATmega161(L) l/O Memory The I/O space definition of the ATmega161 is shown in Table 1. Table 1. ATmega161 I/O Space I/O Address (SRAM Address) Name Function $3F($5F) SREG Status REGister $3E ($5E) Stack Pointer High $3D ($5D) Stack Pointer Low...
Page 20 Table 1. ATmega161 I/O Space (Continued) I/O Address (SRAM Address) Name Function $1C ($3C) EECR EEPROM Control Register $1B($3B) PORTA Data Register, Port A $1A ($3A) DDRA Data Direction Register, Port A $19 ($39) PINA Input Pins, Port A $18 ($38)
Page 21 ATmega161(L) All ATmega161 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general pur- pose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions.
Page 22: Reset And Interrupt Handling
This must be handled by software. Stack Pointer – SP The ATmega161 Stack Pointer is implemented as two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the ATmega161 supports up to 64-Kbyte mem- ory, all 16 bits are used.
Page 23 ATmega161(L) Table 2. Reset and Interrupt Vectors Vector Program Address Source Interrupt Definition $000 RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset $002 INT0 External Interrupt Request 0 $004 INT1 External Interrupt Request 1 $006 INT2 External Interrupt Request 2...
Page 24 ; EEPROM Ready Handler $028 ANA_COMP ; Analog Comparator Handler $02a MAIN: ldi r16,high(RAMEND); Main program start $02b out SPH,r16 $02c ldi r16,low(RAMEND) $02d out SPL,r16 $02e <instr> .org $1e00 $1e00 RESET ; Reset handler … … … … ATmega161(L) 1228B–09/01...
Page 25 ATmega161(L) Reset Sources The ATmega161 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for more than 500 ns.
Page 26 4. Table 4 shows the start-up times from reset. From sleep, only the clock counting part of the start-up time is used. The watchdog oscillator is used for timing the real-time part of the start-up time. The number WDT oscillator cycles used for each time-out is shown in Table 5. ATmega161(L) 1228B–09/01...
Page 27 ATmega161(L) Table 5. Number of Watchdog Oscillator Cycles BODLEVEL Time-out Number of Cycles Unprogrammed 4.2 ms (at V = 2.7V) Unprogrammed 67 ms (at V = 2.7V) Programmed 5.8 ms (at V = 4.0V) Programmed 92 ms (at V = 4.0V) Note: 1.
Page 28 Figure 27. External Reset during Operation Brown-out Detection ATmega161 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and V decreases to a value below the trigger level, the Brown-out Reset is immediately activated.
Page 29 See Bit Description • Bits 7..4 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and always read as zero. • Bit 3 WDRF: Watchdog Reset Flag – This bit is set if a Watchdog reset occurs. The bit is cleared by a Power-on Reset or by writing a logical “0”...
Page 30 Interrupt Handling The ATmega161 has two 8-bit Interrupt Mask control registers; GIMSK (General Inter- rupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register). When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter- rupts are disabled.
Page 31 External Interrupt Request 2 is executed from program memory address $006. See also “External Interrupts.” • Bits 4..0 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and always read as zero. General Interrupt Flag Register – GIFR $3A ($5A) INTF1...
Page 32 Alternatively, the flag can be cleared by writing a logical “1” to it. • Bits 4..0 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and always read as zero. Timer/Counter Interrupt Mask Register – TIMSK $39 ($59)
Page 33 ATmega161(L) • Bit 1 TOIE0: Timer/Counter0 Overflow Interrupt Enable – When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $016) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).
Page 34 The SRE bit overrides any pin direction settings in the respective data direction registers. See Figure 51 through Figure 54 for a descrip- tion of the external memory pin functions. When the SRE bit is cleared (zero), the ATmega161(L) 1228B–09/01...
Page 35 ATmega161(L) external data memory interface is disabled and the normal pin and data direction set- tings are used. • Bit 6 SRW10: External SRAM Wait State – The SRW10 bit is used to set up extra wait states in the external memory interface. See “Double-speed Transmission”...
Page 36 It is possible to configure different wait states for different external memory addresses in ATmega161. The SRL2 - SRL0 bits are used to define at which address the different wait states will be configured. See “Interface to External Memory” on page 82 for a detailed description.
Page 37: Sleep Modes
ATmega161(L) Sleep Modes To enter any of the three sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. The SM1 bit in the MCUCR register and SM0 bit in the EMCUCR register select which sleep mode (Idle, Power-down or Power-save) will be activated by the SLEEP instruction (see Table 6).
Page 38 Timer/Counters The ATmega161 provides three general purpose Timer/Counters – two 8-bit T/Cs and one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an exter- nal oscillator. This oscillator is optimized for use with a 32.768 kHz watch crystal, enabling use of Timer/Counter2 as a Real-time Clock (RTC). Timer/Counters 0 and 1 have individual prescaling selection from the same 10-bit prescaling timer.
Page 39 SFIOR Read/Write Initial Value • Bits 7..2 – Res: Reserved Bits These bits are reserved bits in the ATmega161 and always read as zero. • Bit 1 PSR2: Prescaler Reset Timer/Counter2 – When this bit is set (one), the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed.
Page 40 FLOW IRQ MATCH IRQ TIMER INT. MASK TIMER INT. FLAG T/C0 CONTROL SPECIAL FUNCTIONS REGISTER (TIMSK) REGISTER (TIFR) REGISTER (TCCR0) IO REGISTER (SFIOR) T/C CLEAR TIMER/COUNTER0 T/C CLK SOURCE CONTROL (TCNT0) UP/DOWN LOGIC 8-BIT COMPARATOR OUTPUT COMPARE REGISTER0 (OCR0) ATmega161(L) 1228B–09/01...
Page 41 ATmega161(L) Figure 33. Timer/Counter2 Block Diagram T/C2 OVER- T/C2 COMPARE FLOW IRQ MATCH IRQ 8-BIT DATA BUS 8-BIT ASYNCH T/C2 DATA BUS SPECIAL FUNCTIONS TIMER INT. MASK TIMER INT. FLAG T/C2 CONTROL REGISTER (TCCR2) IO REGISTER (SFIOR) REGISTER (TIMSK) REGISTER (TIFR)
Page 42 Timer/Counter continues counting and is unaffected by a compare match. When a prescaling of 1 is used, and the compare register is set to C, the timer will count as fol- lows if CTC0/CTC2 is set: ... | C-1 | C | 0 | 1 | ... ATmega161(L) 1228B–09/01...
Page 43 ATmega161(L) When the prescaler is set to divide by 8, the timer will count like this: ... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 | 1, 1, 1, ...
Page 44 $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the contents of the Output Compare Register, the PB0(OC0/PWM0) or PB1(OC2/PWM2) pin is set or ATmega161(L) 1228B–09/01...
Page 45 ATmega161(L) cleared according to the settings of the COMn1/COMn0 bits in the Timer/Counter Con- trol Registers TCCR0 or TCCR2. If CTC0/CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PB0(OC0/PWM0) or PB1(OC2/PWM2) pin...
Page 46 Asynchronous Status Register – ASSR $26 ($46) – – – – TCN2UB OCR2UB TCR2UB ASSR Read/Write Initial Value • Bits 7..4 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and always read as zero. ATmega161(L) 1228B–09/01...
Page 47 ATmega161(L) • Bit 3 AS2: Asynchronous Timer/Counter2 Mode – When this bit is cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK. If AS2 is set, the Timer/Counter2 is clocked from the TOSC1 pin. Pins PD4 and PD5 become connected to a crystal oscillator and cannot be used as general I/O pins.
Page 48 1 before the processor can read the timer value, causing the setting of the interrupt flag. The output compare pin is changed on the timer clock and is not synchronized to the processor clock. ATmega161(L) 1228B–09/01...
Page 49 ATmega161(L) Timer/Counter1 Figure 36 shows the block diagram for Timer/Counter1. Figure 36. Timer/Counter1 Block Diagram T/C1 OVER- T/C1 COMPARE T/C1 COMPARE T/C1 INPUT FLOW IRQ MATCHA IRQ MATCHB IRQ CAPTURE IRQ TIMER INT. MASK TIMER INT. FLAG T/C1 CONTROL T/C1 CONTROL...
Page 50 Timer/Counter1. Any output pin actions affect pin OC1B (Output CompareB). This is an alternative function to an I/O port, and the corresponding direc- tion control bit must be set (one) to control an output pin. The following control configuration is given: ATmega161(L) 1228B–09/01...
Page 51 ATmega161(L) Table 14. Compare 1 Mode Select COM1X1 COM1X0 Description Timer/Counter1 disconnected from output pin OC1X Toggle the OC1X output line. Clear the OC1X output line (to zero). Set the OC1X output line (to one). Note: 1. X = A or B In PWM mode, these bits have a different function.
Page 52 Register (ICR1) on the rising edge of the input capture pin (ICP). • Bits 5, 4 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and always read as zero. • Bit 3 CTC1: Clear Timer/Counter1 on Compare Match –...
Page 53 ATmega161(L) The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter1, transitions on PB1/(T1) will clock the counter even if the pin is configured as an output.
Page 54 ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. ATmega161(L) 1228B–09/01...
Page 55 ATmega161(L) The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program and interrupt routine. Timer/Counter1 in PWM Mode...
Page 56 When the OCR1X contains $0000 or TOP, and the up/down PWM mode is selected, the output OC1A/OC1B is updated to low or high on the next compare match according to the settings of COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 19. In ATmega161(L) 1228B–09/01...
Page 57 ATmega161(L) overflow PWM mode, the output OC1A/OC1B is held low or high only when the Output Compare Register contains TOP. Table 19. PWM Outputs OCR1X = $0000 or TOP COM1X1 COM1X0 OCR1X Output OC1X $0000 $0000 Note: 1. X = A or B In overflow PWM mode, the table above is only valid for OCR1X = TOP.
Page 58: Watchdog Timer
Initial Value • Bits 7..5 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and will always read as zero. • Bit 4 WDTOE: Watchdog Turn-off Enable – This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled.
Page 59 ATmega161(L) 1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical “0” to WDE. This disables the watchdog.
Page 60 Initial Value • Bits 15..9 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and will always read as zero. • Bits 8..0 EEAR8..0: EEPROM Address – The EEPROM Address Registers (EEARH and EEARL) specify the EEPROM address in the 512-byte EEPROM space.
Page 61 Initial Value • Bits 7..4 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and will always read as zero. • Bit 3 EERIE: EEPROM Ready Interrupt Enable – When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled.
Page 62 Flash memory cannot be updated by the CPU unless the boot loader software supports writing to the Flash and the Boot Lock bits are configured so that writing to the Flash memory from the CPU is allowed. See “Boot Loader Support” on page 108 for details. ATmega161(L) 1228B–09/01...
Page 63: Serial Peripheral Interface (Spi)
ATmega161(L) Serial Peripheral The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega161 and peripheral devices or between several AVR devices. The Interface – SPI ATmega161 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer •...
Page 64: Ss Pin Functionality
SPI system. If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as master with the SS pin defined as an input, the SPI sys- ATmega161(L) 1228B–09/01...
Page 65: Data Modes
ATmega161(L) tem interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions: 1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the SPI becoming a slave, the MOSI and SCK pins become inputs.
Page 66 ) is shown in Table 23: Table 23. Relationship between SCK and the Oscillator Frequency SPI2X SPR1 SPR0 SCK Frequency /128 Note: 1. When the SPI is configured as slave, the SPI is only guaranteed to work at ATmega161(L) 1228B–09/01...
Page 67 WCOL set (one), and then by accessing the SPI Data Register. • Bits 5..1 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and will always read as zero. • Bit 0 SPI2X: Double SPI Speed Bit –...
Page 68: Data Transmission
UARTs The ATmega161 features two full-duplex (separate receive and transmit registers) Uni- versal Asynchronous Receiver and Transmitters (UARTs). The main features are: • Baud Rate Generator Generates any Baud Rate • High Baud Rates at low XTAL Frequencies • 8 or 9 Bits Data •...
Page 69 ATmega161(L) • A new character has been written to UDRn before the stop bit from the previous character has been shifted out. The shift register is loaded when the stop bit of the character currently being transmitted has been shifted out.
Page 70: Data Reception
Sampling of an incoming character is shown in Figure 47. Note that the description above is not valid when the UART trans- mission speed is doubled. See “Double-speed Transmission” on page 77 for a detailed description. ATmega161(L) 1228B–09/01...
Page 71 ATmega161(L) Figure 47. Sampling Received Data “Double-speed Note: 1. This figure is not valid when the UART speed is doubled. See Transmission” on page 77 for a detailed description. When the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit.
Page 72: Uart Control
UART0 Control and Status Registers – UCSR0A $0B ($2B) RXC0 TXC0 UDRE0 – U2X0 MPCM0 UCSR0A Read/Write Initial Value UART1 Control and Status Registers – UCSR1A $02 ($22) RXC1 TXC1 UDRE1 – U2X1 MPCM1 UCSR1A Read/Write Initial Value ATmega161(L) 1228B–09/01...
Page 73 The ORn bit is cleared (zero) when data is received and transferred to UDRn. • Bit 2 Res: Reserved Bit – This bit is reserved bit in the ATmega161 and will always read as zero. • Bit 1 U2X0/U2X1: Double the UART Transmission Speed –...
Page 74 When CHR9n is set (one), RXB8n is the ninth data bit of the received character. • Bit 0 TXB80/TXB81: Transmit Data Bit 8 – When CHR9n is set (one), TXB8n is the ninth data bit in the character to be transmitted. ATmega161(L) 1228B–09/01...
Page 75: Baud Rate Generator
ATmega161(L) Baud Rate Generator The baud rate generator is a frequency divider that generates baud rates according to the following equation: BAUD --------------------------------- - 16(UBR • BAUD = Baud rate • = Crystal clock frequency • UBR = Contents of the UBRRH and UBRR registers (0 - 4095) •...
Page 76 UART0 Baud Rate Register Low Byte – UBRR0 $09 ($29) UBRR0 Read/Write Initial Value UART1 Baud Rate Register Low Byte – UBRR1 $00 ($20) UBRR1 Read/Write Initial Value UBRRn stores the eight least significant bits of the UART baud rate register. ATmega161(L) 1228B–09/01...
Page 77 ATmega161(L) Double-speed The ATmega161 provides a separate UART mode that allows the user to double the Transmission communication speed. By setting the U2X bit in UART Control and Status Register UCSRnA, the UART speed will be doubled. The data reception will differ slightly from normal mode.
Page 78 UBR = 8 UBR = 9 230400 UBR = 3 UBR = 3 UBR = 4 460800 UBR = 1 UBR = 1 UBR = 2 20.0 912600 UBR = 0 UBR = 0 UBR = 0 20.0 ATmega161(L) 1228B–09/01...
Page 79: Analog Comparator
ATmega161(L) Analog Comparator The Analog Comparator compares the input values on the positive input PB2 (AIN0) and negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher than the voltage on the negative input PB3 (AIN1), the Analog Comparator Output (ACO) is set (one).
Page 80 DDRB register even if the Analog Comparator is enabled. Therefore, it is not recommended to use UART1 if the Analog Comparator is needed in the same application at the same time. See “UARTs” on page 68 for more details. ATmega161(L) 1228B–09/01...
Page 81: Internal Voltage Reference
ATmega161(L) Internal Voltage ATmega161 features an internal voltage reference with a nominal voltage of 1.22V. This reference is used for Brown-out Detection and it can be used as an input to the Analog Reference Comparator. Voltage Reference The voltage reference has a start-up time that may have an influence on the way it should be used.
Page 82 The SRW11 and SRW10 bits control the number of wait states for the upper page of the external memory address space (see Table 27). Note that if the SRL2, SRL1, and SRL0 bits are set to zero, the SRW11 and SRW10 bit settings will define the wait state of the entire SRAM address space. ATmega161(L) 1228B–09/01...
Page 83 ATmega161(L) • Bits 3..2 EMCUCR – SRW01, SRW00: Wait State Select Bits for Lower Page The SRW01 and SRW00 bits control the number of wait states for the lower page of the external memory address space (see Table 27). Table 27. Wait States...
Page 84 The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external). The Data and Address will only change in T4 if ALE is present (the next instruction accesses the RAM). ATmega161(L) 1228B–09/01...
Page 85 ATmega161(L) Figure 52. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1 System Clock Ø Prev. addr. Address [15..8] Address Prev. data Data/Address [7..0] Address Data Prev. data Data/Address [7..0] Address Data Note: 1. SRWn1 = SRW11 (upper page) or SRW01 (lower page), SRWn0 = SRW10 (upper page) or SRW00 (lower page).
Page 86: Using The External Memory Interface
Figure 55. External SRAM Connected to the AVR D[7:0] Port A A[7:0] SRAM A[15:8] Port C For details on the timing for the SRAM interface, please see Figure 84 through Figure 87 and Table 51 through Table 58. ATmega161(L) 1228B–09/01...
Page 87 ATmega161(L) I/O Ports All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintention- ally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Page 88 Push-pull One Output Note: 1. n: 7,6…0, pin number Port A Schematics Note that all port pins are synchronized. The synchronization latch is, however, not shown in the figure. Figure 56. Port A Schematic Diagrams (Pins PA0 - PA7) ATmega161(L) 1228B–09/01...
Page 89 ATmega161(L) Port B Port B is an 8-bit bi-directional I/O port. Three I/O memory address locations are allocated for the Port B, one each for the Data Register – PORTB, $18($38), Data Direction Register – DDRB, $17($37) and the Port B Input Pins –...
Page 90 AIN1, Analog Comparator Negative Input. This pin also serves as the negative input of the on-chip Analog Comparator. TXD1, Transmit Data (Data output pin for the UART1). When the UART1 transmitter is enabled, this pin is configured as an output regardless of the value of DDRB3. ATmega161(L) 1228B–09/01...
Page 91 ATmega161(L) • RXD1/AIN0 Port B, Bit 2 – AIN0, Analog Comparator Positive Input. This pin also serves as the positive input of the on-chip Analog Comparator. RXD1, Receive Data (Data input pin for the UART1). When the UART1 receiver is enabled, this pin is configured as an input regardless of the value of DDRB2.
Page 92: Port B Schematics
Figure 57. Port B Schematic Diagram (Pins PB0 and PB1) DDBn PORTBn COMx0 WRITE PORTB COMx1 WRITE DDRB READ PORTB LATCH COMP. MATCH x READ PORTB PIN READ DDRB PWMx FOCx CSn2 CSn1 CSn0 ATmega161(L) 1228B–09/01...
Page 93 ATmega161(L) Figure 58. Port B Schematic Diagram (Pin PB2) PULL- RESET DDB2 RESET PORTB2 RXEN1 RXD1 WRITE PORTB AIN0 WRITE DDRB READ PORTB LATCH READ PORTB PIN READ DDRB RXD1: UART1 RECEIVE DATA RXEN1: UART1 RECEIVE ENABLE AIN0: ANALOG COMPARATOR POSITIVE INPUT Figure 59.
Page 94 SPI ENABLE Figure 61. Port B Schematic Diagram (Pin PB5) PULL- RESET DDB5 RESET PORTB5 WRITE PORTB MSTR WRITE DDRB READ PORTB LATCH SPI MASTER READ PORTB PIN READ DDRB SPI ENABLE SPE: MSTR MASTER SELECT SPI SLAVE ATmega161(L) 1228B–09/01...
Page 95 ATmega161(L) Figure 62. Port B Schematic Diagram (Pin PB6) PULL- RESET DDB6 RESET PORTB6 WRITE PORTB MSTR WRITE DDRB READ PORTB LATCH SPI SLAVE READ PORTB PIN READ DDRB SPE: SPI ENABLE MASTER SELECT MSTR SPI MASTER Figure 63. Port B Schematic Diagram (Pin PB7)
Page 96 MOS pull-up resistor is activated. To switch the pull-up resistor off, PORTCn has to be cleared (zero) or the pin has to be configured as an output pin. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. ATmega161(L) 1228B–09/01...
Page 97 ATmega161(L) Table 32. DDCn Effects on Port C Pins DDCn PORTCn Pull-up Comment Input Tri-state (high-Z) Input PCn will source current if ext. pulled low Output Push-pull Zero Output Output Push-pull One Output Note: 1. n: 7, 6,…0, pin number Port C Schematics Note that all port pins are synchronized.
Page 98 If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PORTDn is set (one) when configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTDn has ATmega161(L) 1228B–09/01...
Page 99 ATmega161(L) to be cleared (zero) or the pin has to be configured as an output pin. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Table 34. DDDn Bits on Port D Pins...
Page 100 UART0 RECEIVE ENABLE Figure 66. Port D Schematic Diagram (Pin PD1) PULL- RESET DDD1 RESET PORTD1 WRITE PORTD WRITE DDRD TXEN0 READ PORTD LATCH READ PORTD PIN TXD0 READ DDRD TXD0: UART0 TRANSMIT DATA TXEN0: UART0 TRANSMIT ENABLE ATmega161(L) 1228B–09/01...
Page 101 ATmega161(L) Figure 67. Port D Schematic Diagram (Pins PD2 and PD3) WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD 2, 3 0, 1 Figure 68. Port D Schematic Diagram (Pin PD4) PULL- RESET DDD4 RESET PORTD4...
Page 102 WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD ASYNCH SELECT T/C2 Figure 70. Port D Schematic Diagram (Pin PD6) WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD WRITE ENABLE SRE: EXTERNAL SRAM ENABLE ATmega161(L) 1228B–09/01...
Page 103 ATmega161(L) Figure 71. Port D Schematic Diagram (Pin PD7) WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD READ ENABLE SRE: EXTERNAL SRAM ENABLE 1228B–09/01...
Page 104 MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTEn has to be cleared (zero) or the pin has to be configured as an output pin. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. ATmega161(L) 1228B–09/01...
Page 105 ATmega161(L) Table 36. DDEn Bits on Port E Pins DDEn PORTEn Pull-up Comment Input Tri-state (high-Z) Input PEn will source current if ext. pulled low. Output Push-pull Zero Output Output Push-pull One Output Note: 1. n: 2,1,0, pin number. Alternate Functions of Port E The alternate pin configuration is as follows: •...
Page 106 HW CLEAR SW CLEAR ISC2 Figure 73. Port E Schematic Diagram (Pin PE1) PULL- RESET DDE1 RESET PORTE1 WRITE PORTE WRITE DDRE READ PORTE LATCH READ PORTE PIN READ DDRE SRE: XRAM ENABLE ALE: ALE PULSE FROM XRAM ATmega161(L) 1228B–09/01...
Page 107 ATmega161(L) Figure 74. Port E Schematic Diagram (Pin PE2) DDE2 PORTE2 COM1B0 WRITE PORTE COM1B1 WRITE DDRE READ PORTE LATCH COMP. MATCH 1B READ PORTE PIN READ DDRE PWM10 PWM11 FOC1B 1228B–09/01...
Page 108: Memory Programming
Boot Loader Flash section. If no Boot Loader capability is needed, the entire Flash is available for application code. The ATmega161 has two sep- arate sets of Boot Lock bits that can be set independently. This gives the user a unique flexibility to select different levels of protection.
Page 109: Entering The Boot Loader Program
ATmega161(L) • Protect the entire Flash from a software update by the Boot Loader program • Only protect the Boot Loader section from a software update by the Boot Loader program • Only protect the Application Code section from a software update by the Boot Loader program •...
Page 110: Self-Programming The Flash
To execute a page erase, set up the address in the Z-pointer, write “0011” to SPMCR, and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 are ignored. The page address must be written to Z13:Z7. Other bits in the Z-pointer will be ignored during this operation. ATmega161(L) 1228B–09/01...
Page 111 ATmega161(L) Fill the Temporary Buffer To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write “0001” to SPMCR, and execute SPM within four clock cycles after writing SPMCR. The content of Z6:Z1 is used to address the data in the temporary buffer. Z13:Z7 must point to the page that is supposed to be written.
Page 112 Initial Value • Bits 7..4 Res: Reserved Bits – These bits are reserved bits in the ATmega161 and always read as zero. • Bit 3 BLBSET: Boot Lock Bit Set – If this bit is set at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits according to the data in R0.
Page 113 ATmega161(L) Reading the Fuse and Lock It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, Bits from Software load the Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCR. If an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCR, the Lock bits will be written to the destination register.
Page 114 Program Memory The ATmega161 MCU provides six Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 40. The Lock bits Lock Bits can only be erased to “1” with the Chip Erase command.
Page 115: Signature Bytes
ATmega161 inside the user’s system. The program memory array on the ATmega161 is organized as 128 pages of 128 bytes each. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously in either program- ming mode.
Page 116 The bit codings are shown in Table 43. When pulsing WR or OE, the command loaded determines the action executed. The command is a byte where the different bits are assigned functions as shown in Table 44. Figure 76. Parallel Programming ATmega161 RDY/BSY PB7 - PB0 DATA...
Page 117 ATmega161(L) Table 43. XA1 and XA0 Coding Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS1) Load Data (High or low data byte for Flash determined by BS1) Load Command No Action, Idle Table 44.
Page 118 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write sig- nals are reset. K. Repeat “A” through “J” 128 times or until all data have been programmed. ATmega161(L) 1228B–09/01...
Page 119 ATmega161(L) Figure 77. Programming the Flash Waveforms DATA ADDR. LOW ADDR. HIGH DATA LOW XTAL1 RDY/BSY +12V RESET PAGEL Figure 78. Programming the Flash Waveforms (Continued) DATA DATA HIGH XTAL1 RDY/BSY RESET +12V PAGEL Programming the EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to “Pro- gramming the Flash”...
Page 120 2. H: Load Address High Byte ($00 - $01) 3. B: Load Address ($00 - $FF) 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. ATmega161(L) 1228B–09/01...
Page 121 ATmega161(L) Programming the Fuse Bits The algorithm for programming the Fuse bits is as follows (refer to “Programming the Flash” on page 117 for details on command and data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
Page 122: Parallel Programming Characteristics
3. Set OE to “1”. Parallel Programming Figure 80. Parallel Programming Timing Characteristics XLWL XTAL1 XHXL DVXH XLDX Data & Control (DATA, XA0/1, BS1) BVXH PLBX RHBX BVWL PAGEL PHPL WLWH PLWL WLRL RDY/BSY WLRH XLOL OHDZ OLDV DATA ATmega161(L) 1228B–09/01...
Page 123: Serial Downloading
ATmega161(L) = 25 ° C ± 10%, V Table 45. Parallel Programming Characteristics, T = 5V ± (1)(2)(3) Symbol Parameter Units Programming Enable Voltage 11.5 12.5 Programming Enable Current µA Data and Control Valid before XTAL1 High DVXH XTAL1 Pulse Width High...
Page 124 Serial Programming When writing serial data to the ATmega161, data is clocked on the rising edge of SCK. Algorithm When reading data from the ATmega161, data is clocked on the falling edge of SCK. See Figure 81, Figure 82 and Table 49 for timing details.
Page 125 ATmega161(L) before programming the next page. As a chip-erased device contains $FF in WD_FLASH all locations, programming of addresses that are meant to contain $FF can be skipped. See Table 46 for t value. WD_FLASH Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value $FF.
Page 126 5 = Boot Lock Bit11 6 = Boot Lock Bit12 7 = CKSEL0 Fuse 8 = CKSEL1 Fuse 9 = CKSEL2 Fuse A = BODEN Fuse B = BODLEVEL Fuse C = SPIEN Fuse D = BOOTRST Fuse ATmega161(L) 1228B–09/01...
Page 127: Serial Programming Characteristics
ATmega161(L) Serial Programming Figure 82. Serial Programming Timing Characteristics MOSI SLSH OVSH SHOX SHSL MISO SLIV = -40 ° C to 85 ° C, V Table 49. Serial Programming Characteristics, T = 2.7 - 5.5V (unless otherwise noted) Symbol Parameter Units 5.5V...
Page 128: Electrical Characteristics
I/O Pin Pull-up Resistor kΩ Active mode, V = 3V, 4 MHz Idle mode V = 3V, Power Supply Current 4 MHz WDT enabled, V = 3V 15.0 µA Power-down Mode WDT disabled, V = 3V <1 µA ATmega161(L) 1228B–09/01...
Page 129 ATmega161(L) DC Characteristics (Continued) = -40 ° C to 85 ° C, V (1)(2)(3)(4)(5) = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Units Analog Comparator = 5V ACIO Input Offset Voltage Analog Comparator = 5V ACLK Input Leakage Current Analog Comparator = 2.7V...
Page 130: External Clock Drive Waveforms
CLCL High Time CHCX Low Time CLCX Rise Time µs CLCH Fall Time µs CHCL Notes: 1. See “External Data Memory Timing” for a description of how the duty cycle influences the timing for the external data memory. ATmega161(L) 1228B–09/01...
Page 131: External Data Memory Timing
ATmega161(L) External Data Memory Timing Table 51. External Data Memory Characteristics, 4.0 - 5.5 Volts, No Wait State 8 MHz Oscillator Variable Oscillator Symbol Parameter Unit Oscillator Frequency CLCL ALE Pulse Width 1.0t LHLL CLCL Address Valid A to ALE Low 22.5...
Page 132 ALE Low to WR Low 0.5t 0.5t LLWL CLCL CLCL ALE Low to RD Low 0.5t 0.5t LLRL CLCL CLCL Data Setup to RD High DVRH Read Low to Data Valid RLDV Data Hold After RD High RHDX ATmega161(L) 1228B–09/01...
Page 133 ATmega161(L) Table 55. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait State (Continued) 4 MHz Oscillator Variable Oscillator Symbol Parameter Unit RD Pulse Width 1.0t RLRH CLCL Data Setup to WR Low 0.5t DVWL CLCL Data Hold After WR High 0.5t...
Page 134 Data/Address [7..0] Data Prev. data Address Data/Address [7..0] Figure 85. External Memory Timing (SRWn1 = 0, SRWn0 = 1) System Clock Ø Prev. addr. Address Address [15..8] Prev. data Address Data Data/Address [7..0] Data Data/Address [7..0] Prev. data Address ATmega161(L) 1228B–09/01...
Page 135 ATmega161(L) Figure 86. External Memory Timing (SRWn1 = 1, SRWn0 = 0) System Clock Ø Address [15..8] Prev. addr. Address Data/Address [7..0] Prev. data Address Data Data/Address [7..0] Address Data Prev. data Figure 87. External Memory Timing (SRWn1 = 1, SRWn0 = 1) System Clock Ø...
Page 136: Typical Characteristics
= 5V = 25˚C = 85˚C COMMON MODE VOLTAGE (V) Figure 89. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE V = 2.7V = 25˚C = 85˚C COMMON MODE VOLTAGE (V) ATmega161(L) 1228B–09/01...
Page 137 ATmega161(L) Figure 90. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT = 6V = 25˚C Figure 91. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 = 25˚C 1400 = 85˚C 1200 1000 Sink and source capabilities of I/O ports are measured on one pin at a time.
Page 138 Figure 92. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE = 5V = 25˚C = 85˚C Figure 93. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE = 2.7V = 25˚C = 85˚C ATmega161(L) 1228B–09/01...
Page 139 ATmega161(L) Figure 94. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE = 5V = 25˚C = 85˚C Figure 95. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE = 5V = 25˚C...
Page 140 Figure 96. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE = 2.7V = 25˚C = 85˚C Figure 97. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE = 2.7V = 25˚C = 85˚C ATmega161(L) 1228B–09/01...
Page 141 ATmega161(L) Figure 98. I/O Pin Input Threshold vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V = 25˚C Figure 99. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V = 25˚C 0.18 0.16 0.14 0.12 0.08 0.06 0.04...
Page 142: Register Summary
UART1 I/O Data Register page 72 $02 ($22) UCSR1A RXC1 TXC1 UDRE1 U2X1 MPCM1 page 74 $01 ($21) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 CHR91 RXB81 TXB81 page 72 $00 ($20) UBRR1 UART1 Baud Rate Register page 76 ATmega161(L) 1228B–09/01...
Page 143 ATmega161(L) Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag.
Page 144: Instruction Set Summary
(H = 1) then PC ← PC + k + 1 BRHS Branch if Half-carry Flag Set None if (H = 0) then PC ← PC + k + 1 BRHC Branch if Half-carry Flag Cleared None ATmega161(L) 1228B–09/01...
Page 145 ATmega161(L) Instruction Set Summary (Continued) Mnemonic Operands Description Operation Flags # Clocks if (T = 1) then PC ← PC + k + 1 BRTS Branch if T-flag Set None if (T = 0) then PC ← PC + k + 1...
Page 146 Clear T in SREG H ← 1 Set Half-carry Flag in SREG H ← 0 Clear Half-carry Flag in SREG No Operation None SLEEP Sleep (see specific descr. for Sleep function) None Watchdog Reset (see specific descr. for WDR/timer) None ATmega161(L) 1228B–09/01...
Page 147: Ordering Information
ATmega161(L) Ordering Information Speed (MHz) Power Supply Ordering Code Package Operation Range 2.7 - 5.5V ATmega161-4AC Commercial ATmega161-4PC 40P6 (0°C to 70°C) ATmega161-4AI Industrial ATmega161-4PI 40P6 (-40°C to 85°C) 4.0 - 5.5V ATmega161-8AC Commercial ATmega161-8PC 40P6 (0°C to 70°C) ATmega161-8AI...
Page 148: Packaging Information
(TQFP), 10x10mm body, 2.0mm footprint, 0.8mm pitch. Dimension in Millimeters and (Inches)* JEDEC STANDARD MS-026 ACB 12.25(0.482) PIN 1 ID 11.75(0.462) PIN 1 0.45(0.018) 0.80(0.0315) BSC 0.30(0.012) 10.10(0.394) 9.90(0.386) 1.20(0.047) MAX 0.20(0.008) 0˚~7˚ 0.09(0.004) 0.75(0.030) 0.15(0.006) 0.45(0.018) 0.05(0.002) *Controlling dimension: millimetter REV. A 04/11/2001 ATmega161(L) 1228B–09/01...
Page 149 ATmega161(L) 40P6 40P6, 40-lead, Plastic Dual Inline Parkage (PDIP), 0.600" wide Demension in Millimeters and (Inches)* JEDEC STANDARD MS-011 AC 52.71(2.075) 51.94(2.045) 13.97(0.550) 13.46(0.530) 48.26(1.900) REF 4.83(0.190)MAX SEATING PLANE 0.38(0.015)MIN 3.56(0.140) 3.05(0.120) 0.56(0.022) 1.65(0.065) 0.38(0.015) 2.54(0.100)BSC 1.27(0.050) 15.88(0.625) 15.24(0.600) 0º ~ 15º...
Page 150 No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.

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