General Port Pin Schematic Diagram - Atmel ATmega128 Manual

Boundary-scan and
the Two-wire Interface
2467S–AVR–07/09
Figure 125. General Port Pin Schematic diagram
See Boundary-Scan description
for details!
Pxn
The two Two-wire Interface pins SCL and SDA have one additional control signal in the scan-
chain; Two-wire Interface Enable – TWIEN. As shown in
a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general
scan cell as shown in Figure 130
Notes: 1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan
support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in
the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-
scan.
2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to
drive contention.
PUExn
OCxn
IDxn
SLEEP
PUD: PULLUP DISABLE
PUExn: PULLUP ENABLE for pin Pxn
OCxn: OUTPUT CONTROL for pin Pxn
ODxn: OUTPUT DATA to pin Pxn
IDxn: INPUT DATA from pin Pxn
SLEEP: SLEEP CONTROL
is attached to the TWIEN signal.
ATmega128
Q D
DDxn
Q
CLR
RESET
Q D
ODxn
PORTxn
Q
CLR
RESET
SYNCHRONIZER
D Q
D Q
PINxn
Q
L Q
WDx: WRITE DDRx
RDx: READ DDRx
WPx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
CLK : I/O CLOCK
I/O
Figure 126, the TWIEN signal enables
PUD
WDx
RDx
WPx
RRx
RPx
CLK
I/O
257