Algorithm For Using The Adc - Atmel ATmega128 Manual

2467S–AVR–07/09
The recommended values from
rithm in Table 105. Only the DAC and Port Pin values of the Scan Chain are shown. The column
"Actions" describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Table 105. Algorithm for Using the ADC
Step Actions ADCEN
SAMPLE_
1 1
PRELOAD
2 EXTEST 1
3 1
4 1
5 1
Verify the
COMP bit
6 1
scanned
out to be 0
7 1
8 1
9 1
10 1
Verify the
COMP bit
11 1
scanned
out to be 1
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
Table 104 are used unless other values are given in the algo-
DAC MUXEN HOLD
0x200 0x08 1
0x200 0x08 0
0x200 0x08 1
0x123 0x08 1
0x123 0x08 1
0x200 0x08 1
0x200 0x08 0
0x200 0x08 1
0x143 0x08 1
0x143 0x08 1
0x200 0x08 1
ATmega128
PA3. PA3.
PRECH Data Control
1 0 0
1 0 0
1 0 0
1 0 0
0 0 0
1 0 0
1 0 0
1 0 0
1 0 0
0 0 0
1 0 0
hold,max
PA3.
Pullup_
Enable
0
0
0
0
0
0
0
0
0
0
0
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