Alternate Port Functions - Atmel ATmega48PV Manual

11.3

Alternate Port Functions

8025I–AVR–02/09
ing inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset. If low power consumption during reset is
important, it is recommended to use an external pull-up or pull-down. Connecting unused pins
directly to V or GND is not recommended, since this may cause excessive currents if the pin is
CC
accidentally configured as an output.
Most port pins have alternate functions in addition to being general digital I/Os.
shows how the port pin control signals from the simplified
ridden by alternate functions. The overriding signals may not be present in all port pins, but the
figure serves as a generic description applicable to all port pins in the AVR microcontroller
family.
Figure 11-5. Alternate Port Functions
Pxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP: SLEEP CONTROL
PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
ATmega48P/88P/168P/328P
(1)
PUOExn
PUOVxn
1
0
DDOExn
DDOVxn
1
0
PVOExn
PVOVxn
1
0
DIEOExn
DIEOVxn
1
SLEEP
0
SYNCHRONIZER
SET
D Q D
PINxn
L Q
CLR CLR
PUD: PULLUP DISABLE
WDx: WRITE DDRx
RDx: READ DDRx
RRx: READ PORTx REGISTER
WRx: WRITE PORTx
RPx: READ PORTx PIN
WPx: WRITE PINx
clk : I/O CLOCK
I/O
DIxn: DIGITAL INPUT PIN n ON PORTx
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
Figure 11-2 on page 76
PUD
Q D
DDxn
Q
CLR
WDx
RESET
RDx
1
Q D
0
PORTxn
PTOExn
Q
CLR
RESET
WRx
RRx
RPx
Q
Q
clk
I/O
DIxn
AIOxn
Figure 11-5
can be over-
WPx
,
I/O
80