Compare Output Mode, Phase Correct Pwm Mode; Clock Select Bit Description - Atmel ATmega128 Manual

Timer/Counter
Register – TCNT0
Output Compare
Register – OCR0
ATmega128
106
Table 55. Compare Output Mode, Phase Correct PWM Mode
COM01 COM00 Description
0 0 Normal port operation, OC0 disconnected.
0 1 Reserved
1 0 Clear OC0 on compare match when up-counting. Set OC0 on compare
match when downcounting.
1 1 Set OC0 on compare match when up-counting. Clear OC0 on compare
match when downcounting.
Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare
match is ignored, but the set or clear is done at TOP. See
101 for more details.
• Bit 2:0 – CS02:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see
56.
Table 56. Clock Select Bit Description
CS02 CS01
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Bit 7 6
Read/Write R/W R/W
Initial Value 0 0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a compare match between TCNT0 and the OCR0 Register.
Bit 7 6
Read/Write R/W R/W
Initial Value 0 0
The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an output compare interrupt, or to
generate a waveform output on the OC0 pin.
CS00 Description
0 No clock source (Timer/Counter stopped)
clk
1 /(No prescaling)
T0S
clk
0 /8 (From prescaler)
T0S
clk
/32 (From prescaler)
1
T0S
clk
0 /64 (From prescaler)
T0S
clk
1 /128 (From prescaler)
T0S
0 clk /256 (From prescaler)
0
T S
1 clk /1024 (From prescaler)
0
T S
5 4 3
TCNT0[7:0]
R/W R/W R/W
0 0 0
5 4 3
OCR0[7:0]
R/W R/W R/W
0 0 0
(1)
"Phase Correct PWM Mode" on page
2 1 0
TCNT0
R/W R/W R/W
0 0 0
2 1 0
R/W R/W R/W
0 0 0
Table
OCR0
2467S–AVR–07/09