Page 1: Features
– Power On Reset and Programmable Brown Out Detection – In-System Programmable via SPI Port – High Precision Crystal Oscillator for CAN Operations (16MHz) ® See certification on Atmel web site and note on “Baud Rate” on page 177. 7647H–AVR–03/12...
Page 2 Core Speed Grade: – 0 - 8MHz at 2.7 - 4.5V – 0 - 16MHz at 4.5 - 5.5V ATmega32/64/M1/C1 Product Line-up Part Number ATmega32C1 ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 Flash Size 32 Kbyte 64 Kbyte 16 Kbyte 32 Kbyte 64 Kbyte...
Page 3: Pin Configurations
Atmel ATmega16/32/64/M1/C1 1. Pin Configurations Figure 1-1. ATmega16/32/64M1 TQFP32/QFN32 (7*7 mm) Package. ATmega32/64M1 TQFP32/QFN32 (PCINT18/PSCIN2/OC1A/MISO_A) PD2 PB4 (AMP0+/PCINT4) (PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3 PB3 (AMP0-/PCINT3) (PCINT9/PSCIN1/OC1B/SS_A) PC1 PC6 (ADC10/ACMP1/PCINT14) AREF(ISRC) AGND AVCC (PCINT10/T0/TXCAN) PC2 PC5 (ADC9/ACMP3/AMP1+/PCINT13) (PCINT11/T1/RXCAN/ICP1B) PC3 PC4 (ADC8/ACMPN3/AMP1-/PCINT12) (PCINT0/MISO/PSCOUT2A) PB0 Note: On the engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located on PC4.
Page 4 PC6 (ADC10/ACMP1/PCINT14) AREF(ISRC) AGND (PCINT10/T0/TXCAN) PC2 AVCC PC5 (ADC9/ACMP3/AMP1+/PCINT13) (PCINT11/T1/RXCAN/ICP1B) PC3 PC4 (ADC8/ACMPN3/AMP1-/PCINT12) (PCINT0/MISO) PB0 Note: On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located on PC4. It is located on PE2. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 5: Pin Descriptions
Atmel ATmega16/32/64/M1/C1 Pin Descriptions Table 1-1. Pin out description QFN32 Pin Number Mnemonic Type Name, Function and Alternate Function Power Ground: 0V reference AGND Power Analog Ground: 0V reference for analog part Power Power Supply Analog Power Supply: This is the power supply voltage for...
Page 6 MISO_A (Programming & alternate SPI Master In Slave Out) PCINT18 (Pin Change Interrupt 18) Note: 1. On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located on PC4. It is located on PE2. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 7 Atmel ATmega16/32/64/M1/C1 Table 1-1. Pin out description (Continued) QFN32 Pin Number Mnemonic Type Name, Function and Alternate Function TXD (UART Tx data) TXLIN (LIN Transmit Output) OC0A (Timer 0 Output Compare A) SS (SPI Slave Select) MOSI_A (Programming & alternate Master Out SPI Slave In)
Page 8: Overview
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 9: Automotive Quality Grade
Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16/32/64/M1/C1 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
Page 10: Pin Descriptions
Reset, even if the clock is not running. The minimum pulse length is given in Table 7-1 on page 47. Shorter pulses are not guaranteed to generate a Reset. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 11: About Code Examples
Atmel ATmega16/32/64/M1/C1 Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscil- lator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PE2 can be used as output from the inverting Oscillator amplifier.
Page 12: Avr Cpu Core
While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 13: Alu - Arithmetic Logic Unit
Atmel ATmega16/32/64/M1/C1 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ- ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File –...
Page 14: Status Register
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 15: General Purpose Register File
Atmel ATmega16/32/64/M1/C1 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve...
Page 16: Stack Pointer
AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. SP15 SP14 SP13 SP12 SP11 SP10 Read/Write Initial Value Top address of the SRAM (0x04FF/0x08FF/0x10FF) Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 17: Instruction Execution Timing
Atmel ATmega16/32/64/M1/C1 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk , directly generated from the selected clock source for the chip. No internal clock division is used.
Page 18 When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 19 Atmel ATmega16/32/64/M1/C1 Assembly Code Example in r16, SREG ; store SREG value ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG;...
Page 20: Memories
– Load Program Memory. Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim- ing” on page Figure 4-1. Program Memory Map Program Memory 0x0000 Application F lash Sec t ion Boot Flash S e ction 0x1FFF/0x3FFF/0x7F Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 21: Sram Data Memory
Atmel ATmega16/32/64/M1/C1 SRAM Data Memory Figure 4-2 shows how the ATmega16/32/64/M1/C1 SRAM Memory is organized. The ATmega16/32/64/M1/C1 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Page 22: Eeprom Data Memory
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 23 Atmel ATmega16/32/64/M1/C1 4.3.2 The EEPROM Address Registers – EEARH and EEARL – – – – – EEAR10 EEAR9 EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL Read/Write Initial Value • Bits 15.11 – Reserved Bits These bits are reserved bits in the ATmega16/32/64/M1/C1 and will always read as zero.
Page 24 When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 25 Atmel ATmega16/32/64/M1/C1 • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read.
Page 26 & (1<<EEWE)) /* Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 27 Atmel ATmega16/32/64/M1/C1 The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write...
Page 28: I/O Memory
General Purpose I/O Register 1 – GPIOR1 GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10 GPIOR1 Read/Write Initial Value 4.5.3 General Purpose I/O Register 2 – GPIOR2 GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 GPIOR2 Read/Write Initial Value Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 29: System Clock
Atmel ATmega16/32/64/M1/C1 5. System Clock Clock Systems and their Distribution Figure 5-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described in “Power Management and...
Page 30: Clock Sources
The number of WDT Oscillator cycles used for each time-out is shown in Table 5-2. The frequency of the Watchdog Oscillator is voltage dependent as shown in “Watchdog Oscillator Frequency versus V ” on page 342. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 31: Default Clock Source
Atmel ATmega16/32/64/M1/C1 Table 5-2. Number of Watchdog Oscillator Cycles Typ Time-out (V = 5.0V) Typ Time-out (V = 3.0V) Number of Cycles 4.1 ms 4.3 ms 4K (4,096) 65 ms 69 ms 64K (65,536) Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of 8.
Page 32 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 33: Calibrated Internal Rc Oscillator
Atmel ATmega16/32/64/M1/C1 Calibrated Internal RC Oscillator By default, the Internal RC OScillator provides an approximate 8.0MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler”...
Page 34: Pll
The internal PLL is enabled only when the PLLE bit in the register PLLCSR is set. The bit PLOCK from the register PLLCSR is set when PLL is locked. Both internal 8MHz RC Oscillator, Crystal Oscillator and PLL are switched off in Power-down and Standby sleep modes.03/12 Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 35 Atmel ATmega16/32/64/M1/C1 Table 5-7. Start-up Times when the PLL is selected as system clock CKSEL Start-up Time from Power-down Additional Delay from Reset 3..0 SUT1..0 and Power-save = 5.0V) 1K CK 14CK 1K CK 14CK + 4 ms 0011 RC Osc...
Page 36: 128 Khz Internal Oscillator
5-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 5-4. External Clock Drive Configuration XTAL2 External XTAL1 Clock Signal Table 5-8. External Clock Frequency CKSEL3..0 Frequency Range 0000 0 - 16MHz Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 37: Clock Output Buffer
Atmel ATmega16/32/64/M1/C1 When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 5-9. Table 5-9. Start-up Times for the External Clock Selection Start-up Time from Additional Delay from SUT1..0 Power-down and Power-save Reset (V = 5.0V)
Page 38 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selcted clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 39 Atmel ATmega16/32/64/M1/C1 Table 5-10. Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor Reserved Reserved Reserved Reserved Reserved Reserved Reserved 7647H–AVR–03/12...
Page 40: Power Management And Sleep Modes
To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 41: Idle Mode
Atmel ATmega16/32/64/M1/C1 Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, UART, Analog Comparator, ADC, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halt clk and clk , while allowing the other clocks to run.
Page 42: Standby Mode
So its recommended to stop a peripheral before stopping its clock with PRR register. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 43 Atmel ATmega16/32/64/M1/C1 6.6.1 Power Reduction Register - PRR PRCAN PRPSC PRTIM1 PRTIM0 PRSPI PRLIN PRADC Read/Write Initial Value • Bit 7 - Res: Reserved Bit This bit is unused bit in the ATmega16/32/64/M1/C1, and will always read as zero. • Bit 6 - PRCAN: Power Reduction CAN Writing a logic one to this bit reduces the consumption of the CAN by stopping the clock to this module.
Page 44: Minimizing Power Consumption
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consump- tion. Refer to “Watchdog Timer” on page 52 for details on how to configure the Watchdog Timer. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 45 Atmel ATmega16/32/64/M1/C1 6.7.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk...
Page 46: System Control And Reset
Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. • Brown-out Reset. The MCU is reset when the supply voltage V is below the Brown-out Reset threshold (V ) and the Brown-out Detector is enabled. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 47 Atmel ATmega16/32/64/M1/C1 Figure 7-1. Reset Logic DATA BUS MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor Spike Filter Watchdog Oscillator Delay Counters Clock TIMEOUT Generator CKSEL[3:0] SUT[1:0] Table 7-1. Reset Characteristics Symbol Parameter Units...
Page 48 Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V – on its positive edge, the delay counter starts the MCU after the Time-out period – t – has expired. TOUT Figure 7-4. External Reset During Operation Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 49 Atmel ATmega16/32/64/M1/C1 7.2.3 Brown-out Detection ATmega16/32/64/M1/C1 has an On-chip Brown-out Detection (BOD) circuit for monitoring the level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection.
Page 50 • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 51: Internal Voltage Reference
Atmel ATmega16/32/64/M1/C1 • Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs.
Page 52: Watchdog Timer
WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 53 Atmel ATmega16/32/64/M1/C1 The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.
Page 54 1. The example code assumes that the part specific header file is included. Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period; Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 55 Atmel ATmega16/32/64/M1/C1 7.4.1 Watchdog Timer Control Register - WDTCSR WDIF WDIE WDP3 WDCE WDP2 WDP1 WDP0 WDTCSR Read/Write Initial Value • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config- ured for interrupt.
Page 56 64 ms 16K (16384) cycles 0.125 s 32K (32768) cycles 0.25 s 64K (65536) cycles 0.5 s 128K (131072) cycles 1.0 s 256K (262144) cycles 2.0 s 512K (524288) cycles 4.0 s 1024K (1048576) cycles 8.0 s Reserved Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 57: Interrupts
Atmel ATmega16/32/64/M1/C1 8. Interrupts T h i s s e c t i o n d e s c r i b e s t h e s p e c i f i c s o f t h e i n t e r r u p t h a n d l i n g a s p e r f o r m e d i n ATmega16/32/64/M1/C1.
Page 58 ; Timer0 Overflow Handler 0x024 CAN_INT ; CAN MOB,Burst,General Errors Handler 0x026 CAN_TOVF ; CAN Timer Overflow Handler 0x028 LIN_TC ; LIN Transfer Complete Handler 0x02A LIN_ERR ; LIN Error Handler 0x02C PCINT0 ; Pin Change Int Request 0 Handler Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 59 Atmel ATmega16/32/64/M1/C1 0x02E PCINT1 ; Pin Change Int Request 1 Handler 0x030 PCINT2 ; Pin Change Int Request 2 Handler 0x032 PCINT3 ; Pin Change Int Request 3 Handler 0x034 SPI_STC ; SPI Transfer Complete Handler 0x036 ; ADC Conversion Complete Handler 0x038 ;...
Page 60 Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 61 Atmel ATmega16/32/64/M1/C1 Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Page 62: I/O-Ports
67. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 63: Ports As General Digital I/O
Atmel ATmega16/32/64/M1/C1 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 9-2 shows a func- tional description of one I/O-port pin, here generically called Pxn. Figure 9-2. General Digital I/O DDxn RESET PORTxn...
Page 64 Figure 9-3 shows a timing dia- gram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t and t respectively. pd,max pd,min Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 65 Atmel ATmega16/32/64/M1/C1 Figure 9-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS in r17, PINx SYNC LATCH PINxn 0x00 0xFF pd, max pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH”...
Page 66 “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 67: Alternate Port Functions
Atmel ATmega16/32/64/M1/C1 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 9-5 shows how the port pin control signals from the simplified Figure 9-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.
Page 68 The signal is connected directly to the pad, and can be used Input/Output bi-directionally. The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 69 Atmel ATmega16/32/64/M1/C1 9.3.1 MCU Control Register – MCUCR SPIPS – – – – IVSEL IVCE MCUCR Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
Page 70 DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 and PUD bits. PSCOUT2B, Output 2B of PSC. PCINT1, Pin Change Interrupt 1. • PCINT0/MISO/PSCOUT2A – Bit 0 Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 71 Atmel ATmega16/32/64/M1/C1 MISO, Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB0. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 and PUD bits.
Page 72 AMP2+, Analog Differential Amplifier 2 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Amplifier. PCINT15, Pin Change Interrupt 15. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 73 Atmel ATmega16/32/64/M1/C1 • ADC10/ACMP1/PCINT14 – Bit 6 ADC10, Analog to Digital Converter, input channel 10. ACMP1, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Ana- log Comparator.
Page 74 Overriding Signals for Alternate Functions in PC3..PC0 PC1/PSCIN1/ PC0/INT3/ PC3/T1/RXCAN/ PC2/T0/TXCAN/ OC1B/SS_A/ PSCOUT1A/ Signal Name ICP1B/PCINT11 PCINT10 PCINT9 PCINT8 PUOE PUOV DDOE PSCen10 DDOV PVOE OC1Ben PSCen10 PVOV OC1B PSCout10 DIEOE In3en DIEOV In3en PSCin1 INT3 SS_A Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 75 Atmel ATmega16/32/64/M1/C1 9.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 9-9. Table 9-9. Port D Pins Alternate Functions Port Pin Alternate Function ACMP0 (Analog Comparator 0 Positive Input ) PCINT23 (Pin Change Interrupt 23)
Page 76 DDD3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTD3 bit. PCINT19, Pin Change Interrupt 19. • PCINT18/PSCIN2/OC1A/MISO_A, Bit 2 PCSIN2, PSC Digital Input 2. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 77 Atmel ATmega16/32/64/M1/C1 OC1A, Output Compare Match A output: This pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD2 set “one”) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.
Page 78 PCINT25 (Pin Change Interrupt 25) RESET# (Reset Input) OCD (On Chip Debug I/O) PCINT24 (Pin Change Interrupt 24) Note: On the engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located on PC4. It is located on PE2. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 79 Atmel ATmega16/32/64/M1/C1 The alternate pin configuration is as follows: • PCINT26/XTAL2/ADC0 – Bit 2 XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
Page 80: Register Description For I/O-Ports
Port D Data Register – PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD Read/Write Initial Value 9.4.8 Port D Data Direction Register – DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read/Write Initial Value Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 81 Atmel ATmega16/32/64/M1/C1 9.4.9 Port D Input Pins Address – PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND Read/Write Initial Value 9.4.10 Port E Data Register – PORTE – – – – – PORTE2 PORTE1 PORTE0 PORTE Read/Write Initial Value 9.4.11...
Page 82: External Interrupts
An example of timing of a pin change interrupt is schown in Figure 10-1. Figure 10-1. Timing of a pin change interrupts pcint_sync pcint_set/flag pin_lat pin_sync pcint_in[i] PCINT[i] PCIF (interrupt flag) PCINT[i] bit (of PCMSK PCINT[i] pin pin_lat pin_sync pcint_in[i] pcint_syn pcint_set/flag PCIF Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 83: External Interrupt Control Register A - Eicra
Atmel ATmega16/32/64/M1/C1 10.2 External Interrupt Control Register A – EICRA The External Interrupt Control Register A contains control bits for interrupt sense control. ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 EICRA Read/Write Initial Value • Bit 7..0 – ISC31, ISC30 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set.
Page 84 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter- rupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 85 Atmel ATmega16/32/64/M1/C1 10.2.4 Pin Change Interrupt Flag Register - PCIFR – – – – PCIF3 PCIF2 PCIF1 PCIF0 PCIFR Read/Write Initial Value • Bit 7..4 - Res: Reserved Bits These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero.
Page 86 If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 87: Timer/Counter0 And Timer/Counter1 Prescalers
Atmel ATmega16/32/64/M1/C1 11. Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 11.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This...
Page 88 When the TSM bit is written to zero, the PSRSYNC bit is cleared by hardware, and the Timer/Counters start counting simultaneously. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 89 Atmel ATmega16/32/64/M1/C1 • Bit6 – ICPSEL1: Timer 1 Input Capture selection Timer 1 capture function has two possible inputs ICP1A (PD4) and ICP1B (PC3). The selection is made thanks to ICPSEL1 bit as described in Table 11-1. Table 11-1. ICPSEL1...
Page 90: 12 8-Bit Timer/Counter0 With Pwm
Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 91: Timer/Counter Clock Sources
Atmel ATmega16/32/64/M1/C1 The definitions in Table 12-1 are also used extensively throughout the document. Table 12-1. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x00. The counter reaches its MAXimum when it becomes 0xFF (decimal 255). The counter reaches the TOP when it becomes equal to the highest value in the count sequence.
Page 92: Output Compare Unit
Waveform Generator for handling the special cases of the extreme values in some modes of operation (“Modes of Operation” on page 95). Figure 12-3 shows a block diagram of the Output Compare unit. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 93 Atmel ATmega16/32/64/M1/C1 Figure 12-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn (8-bit Comparator ) OCFnx (Int.Req.) bottom Waveform Generator OCnx FOCn WGMn1:0 COMnx1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is disabled.
Page 94: Compare Match Output Unit
The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter Register Description” on page 101. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 95: Modes Of Operation
Atmel ATmega16/32/64/M1/C1 12.5.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next compare match.
Page 96 This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 97 Atmel ATmega16/32/64/M1/C1 In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 12-6.
Page 98 (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 99: Timer/Counter Timing Diagrams
Atmel ATmega16/32/64/M1/C1 In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set.
Page 100 OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- caler (f clk_I/O (clk TCNTn TOP - 1 BOTTOM BOTTOM + 1 (CTC) OCRnx OCFnx Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 101: 8-Bit Timer/Counter Register Description
Atmel ATmega16/32/64/M1/C1 12.8 8-bit Timer/Counter Register Description 12.8.1 Timer/Counter Control Register A – TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to.
Page 102 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 96 for more details. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 103 Atmel ATmega16/32/64/M1/C1 Table 12-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor- rect PWM mode. Table 12-7. Compare Output Mode, Phase Correct PWM Mode COM0B1 COM0B0 Description Normal port operation, OC0B disconnected. Reserved Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting.
Page 104 No clock source (Timer/Counter stopped) /(No prescaling) /8 (From prescaler) /64 (From prescaler) /256 (From prescaler) /1024 (From prescaler) External clock source on T0 pin. Clock on falling edge. External clock source on T0 pin. Clock on rising edge. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 105 Atmel ATmega16/32/64/M1/C1 If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 12.8.3 Timer/Counter Register – TCNT0...
Page 106 When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 12-8, “Waveform Generation Mode Bit Description” on page 103. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 107: 16-Bit Timer/Counter1 With Pwm
Atmel ATmega16/32/64/M1/C1 13. 16-bit Timer/Counter1 with PWM The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units •...
Page 108 Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 109: Accessing 16-Bit Registers
Atmel ATmega16/32/64/M1/C1 The double buffered Output Compare Registers (OCRnx) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OCnx).
Page 110 Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 111 Atmel ATmega16/32/64/M1/C1 The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnx or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: ; Save global interrupt flag in r18,SREG ;...
Page 112: Timer/Counter Clock Sources
Clock Select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter control Register B (TCCRnB). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 113: Counter Unit
Atmel ATmega16/32/64/M1/C1 13.4 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 13-2 shows a block diagram of the counter and its surroundings. Figure 13-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.)
Page 114: Input Capture Unit
(ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 115 Atmel ATmega16/32/64/M1/C1 The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera- tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn Register.
Page 116: Output Compare Units
(n = n for Timer/Counter n), and the “x” indicates Output Compare unit (x). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 117 Atmel ATmega16/32/64/M1/C1 Figure 13-4. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) OCRnx Buffer (16-bit Register) TCNTn (16-bit Counter) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) (16-bit Comparator ) OCFnx (Int.Req.)
Page 118: Compare Match Output Unit
(DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a system reset occur, the OCnx Register is reset to “0”. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 119 Atmel ATmega16/32/64/M1/C1 Figure 13-5. Compare Match Output Unit, Schematic COMnx1 Waveform COMnx0 Generator FOCnx OCnx OCnx PORT The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin.
Page 120: Modes Of Operation
The timing diagram for the CTC mode is shown in Figure 13-6. The counter value (TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 121 Atmel ATmega16/32/64/M1/C1 Figure 13-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (COMnA1:0 = 1) (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value.
Page 122 TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCRnA Register however, is double buffered. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 123 Atmel ATmega16/32/64/M1/C1 This feature allows the OCRnA I/O location to be written anytime. When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNTn matches TOP.
Page 124 Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCRnx Registers are written. As the third period shown in Figure 13-8 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 125 Atmel ATmega16/32/64/M1/C1 The reason for this can be found in the time of update of the OCRnx Register. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value.
Page 126 When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 127 Atmel ATmega16/32/64/M1/C1 Figure 13-9 shows the output generated is, in contrast to the phase correct mode, symmetri- cal in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct.
Page 128: Timer/Counter Timing Diagrams
Figure 13-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f clk_I/O (clk TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 129 Atmel ATmega16/32/64/M1/C1 Figure 13-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
Page 130: 16-Bit Timer/Counter Register Description
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 121. for more details. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 131 Atmel ATmega16/32/64/M1/C1 Table 13-3 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 13-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct COMnA1/COMnB1...
Page 132 No clock source (Timer/Counter stopped). /1 (No prescaling) /8 (From prescaler) /64 (From prescaler) /256 (From prescaler) /1024 (From prescaler) External clock source on Tn pin. Clock on falling edge. External clock source on Tn pin. Clock on rising edge. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 133 Atmel ATmega16/32/64/M1/C1 If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 13.10.3 Timer/Counter1 Control Register C – TCCR1C...
Page 134 When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (Table 8-2 on page 58) is executed when the OCF1B Flag, located in TIFR1, is set. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 135 Atmel ATmega16/32/64/M1/C1 • Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding...
Page 136: Power Stage Controller - (Psc) (Only Atmega16/32/64M1)
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 137: Psc Description
Atmel ATmega16/32/64/M1/C1 14.4 PSC Description Figure 14-1. Power Stage Controller Block Diagram PSC Counter Prescaler POCR0RB module 0 Waveform Generator B PSCOUT0B POCR0SB (Analog Comparator 0 Ouput) AC0O Overlap PSC Input 0 Protection POCR0RA PSCIN0 PISEL0 Waveform Generator A PSCOUT0A...
Page 138: Functional Description
The PSC can be configured in one of two modes (1Ramp Mode or Centered Mode). This config- uration will affect the operation of all the waveform generators. Figure 14-2. Cycle Presentation in One Ramp Mode One PSC Cycle Sub-Cycle A Sub-Cycle B PSC Counter Value UPDATE Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 139 Atmel ATmega16/32/64/M1/C1 Figure 14-3. Cycle Presentation in Centered Mode One PSC Cycle PSC Counter Value UPDATE Figure 14-2 Figure 14-3 graphically illustrate the values held in the PSC counter. Centered Mode is like One Ramp Mode which counts down and then up.
Page 140 Dead-Time B = (POCRnSBH/L - POCRnRAH/L) * 1/Fclkpsc Minimal value for Dead-Time A = 1/Fclkpsc If the overlap protection is disabled, in One-Ramp mode, PSCOUTnA and PSCOUTnB outputs can be configured to overlap each other, though in normal use this is not desirable. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 141 Atmel ATmega16/32/64/M1/C1 Figure 14-5. Controlled Start and Stop Mechanism in One-Ramp Mode POCRnRB POCRnSB POCRnRA POCRnSA PSC Counter PSCOUTnA PSCOUTnB Note: See “PSC Control Register – PCTL” on page 154. (PCCYC = 1) 14.5.3.2 Center Aligned Mode In center aligned mode, the center of PSCOUTnA and PSCOUTnB signals are centered.
Page 142: Update Of Values
With Set i With Set i With Set i With Set i Cycle With Set j End of Cycle The software can stop the cycle before the end to update the values and restart a new PSC cycle. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 143: Overlap Protection
For ATmega16/64M1, and ATmega32M1 since rev C, the overlap protection is activated with only one condition: 1. POVENn=0 (PSC Module n Overlap Enable) Up to rev B of ATmega32M1, the overlap protection was activated with the 2 following conditions: 2. POVENn=0 (PSC Module n Overlap Enable) 3.
Page 144: Signal Description
14.8 Signal Description Figure 14-9. PSC External Block View POCRRB[11:0] PSCOUT0A PSCOUT0B POCR0SB[11:0] PSCOUT1A POCR0RA[11:0] PSCOUT1B POCR0SA[11:0] PSCOUT2A POCR1SB[11:0] PSCOUT2B POCR1RA[11:0] AC2O POCR1SA[11:0] AC1O POCR2SB[11:0] AC0O POCR2RA[11:0] PSCIN2 PSCIN1 POCR2SA[11:0] PSCIN0 IRQ PSC PSCASY Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 145 Atmel ATmega16/32/64/M1/C1 14.8.1 Input Description Table 14-1. Internal Inputs Type Name Description Width Register Compare Value which Reset Signal on Part B POCR_RB[11:0] (PSCOUTnB) 12 bits Register POCRnSB[11:0] Compare Value which Set Signal on Part B (PSCOUTnB) 12 bits Register...
Page 146: Psc Input
For detailed information on the PSC, please refer to Application Note ‘AVR138: PSC Cookbook’, available on the Atmel web site. Each module 0, 1 and 2 of PSC has its own system to take into account one PSC input. Accord- ing to PSC Module n Input Control Register (See “PSC Module n Input Control Register –...
Page 147 Atmel ATmega16/32/64/M1/C1 Figure 14-11. PSC Input Filterring Digital PSC Module n Input Filter 4 x CLK PSC Input Ouput PSCOUTnX Module X Stage 14.9.1.2 Signal Polarity One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit description in Section "PSC Module n Input Control Register –...
Page 148: Psc Input Modes 001B To 10Xb: Deactivate Outputs Without Changing Timing
14.11 PSC Input Mode 11xb: Halt PSC and Wait for Software Action Figure 14-14. PSC behaviour versus PSCn Input A in Fault Mode 11xb DT0 OT0 PSCOUTnA PSCOUTnB PSCn Input Software Action (1) Note: Software action is the setting of the PRUNn bit in PCTLn register. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 149: Analog Synchronization
Atmel ATmega16/32/64/M1/C1 Used in Fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 14.12 Analog Synchronization Each PSC module generates a signal to synchronize the ADC sample and hold; synchronisation is mandatory for measurements.
Page 150: Interrupts
• PSC_Fault (Fault Event): When enabled and when a PSC input detects a Fault event. 14.15.2 PSC Interrupt Vectors in ATmega16/32/64/M1/C1 Table 14-7. PSC Interrupt Vectors Vector Program Address Source Interrupt Definition 0x0004 PSC_Fault PSC Fault event 0x0005 PSC_End PSC End of Cycle Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 151: Psc Register Definition
Atmel ATmega16/32/64/M1/C1 14.16 PSC Register Definition Registers are explained for PSC module 0. They are identical for module 1 and module 2. 14.16.1 PSC Output Configuration – POC POEN2B POEN2A POEN1B POEN1A POEN0B POEN0A Read/Write Initial Value • Bit 7 – not use not use •...
Page 152 Send signal on match with OCRnRA (during counting down of PSC). The min value of OCRnRA must be 1. Send signal on match with OCRnRA (during counting up of PSC). The min value of OCRnRA must be 1. no synchronization signal no synchronization signal Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 153 Atmel ATmega16/32/64/M1/C1 14.16.3 PSC Output Compare SA Register – POCRnSAH and POCRnSAL – – – – POCRnSA[11:8] POCRnSAH POCRnSA[7:0] POCRnSAL Read/Write Initial Value 14.16.4 PSC Output Compare RA Register – POCRnRAH and POCRnRAL – – – – POCRnRA[11:8] POCRnRAH POCRnRA[7:0]...
Page 154 • Bit 5 – PCLKSEL: PSC Input Clock Select This bit is used to select between CLK or CLK clocks. Set this bit to select the fast clock input (CLK Clear this bit to select the slow clock input (CLK Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 155 Atmel ATmega16/32/64/M1/C1 • Bit 4:3:2 – SWAPn: SWAP Funtion Select (not implemented in ATmega32M1 up to revision C) When this bit is set; the channels PSCOUTnA and PSCOUTnB are exchanged. This allows to invert the waveforms of both channels at one time.
Page 156 When this bit is set, an external event which can generates a fault on module 0 generates also an interrupt. • Bit 0 – PEOPE : PSC End Of Cycle Interrupt Enable When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 157 Atmel ATmega16/32/64/M1/C1 14.16.11 PSC Interrupt Flag Register – PIFR PEV2 PEV1 PEV0 PEOP PIFR Read/Write Initial Value • Bit 7:4 – not use not use. • Bit 3 – PEV2 : PSC External Event 2 Interrupt This bit is set by hardware when an external event which can generates a fault on module 2 occurs.
Page 158: Serial Peripheral Interface - Spi
Double Speed (CK/2) Master SPI Mode Figure 15-1. SPI Block Diagram SPIPS MISO MISO MOSI MOSI DIVIDER /2/4/8/16/32/64/128 SS_A Note: 1. Refer to Figure 1-1 on page 3, and Table 9-3 on page 69 for SPI pin placement. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 159 Atmel ATmega16/32/64/M1/C1 The interconnection between Master and Slave CPUs with SPI is shown in Figure 15-2. The sys- tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
Page 160 DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and DDR_SPI with DDRB. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 161 Atmel ATmega16/32/64/M1/C1 Assembly Code Example SPI_MasterInit: ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) SPCR,r17 SPI_MasterTransmit: ; Start transmission of data (r16) SPDR,r16 Wait_Transmit: ; Wait for transmission complete...
Page 162 /* Enable SPI */ SPCR = (1<<SPE); char SPI_SlaveReceive(void) /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return data register */ return SPDR; Note: 1. The example code assumes that the part specific header file is included. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 163: Ss Pin Functionality
Atmel ATmega16/32/64/M1/C1 15.2 SS Pin Functionality 15.2.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs.
Page 164 Figure 15-4 for an example. The CPOL functionality is summarized below: Table 15-3. CPHA Functionality CPHA Leading Edge Trailing Edge Sample Setup Setup Sample • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 165 Atmel ATmega16/32/64/M1/C1 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the clk frequency f is shown in clkio the following table: Table 15-4.
Page 166: Data Modes
CHANGE 0 MISO PIN MSB first (DORD = 0) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first (DORD = 1) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 167 Atmel ATmega16/32/64/M1/C1 Figure 15-4. SPI Transfer Format with CPHA = 1 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN MSB first (DORD = 0) Bit 6...
Page 168: Controller Area Network - Can
The priorities are laid down during system design in the form of corresponding binary values and cannot be changed dynamically. The identifier with the lowest binary number has the highest priority. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 169 Atmel ATmega16/32/64/M1/C1 Bus access conflicts are resolved by bit-wise arbitration on the identifiers involved by each node observing the bus level bit for bit. This happens in accordance with the "wired and" mechanism, by which the dominant state overwrites the recessive state. The competition for bus allocation is lost by all nodes with recessive transmission and dominant observation.
Page 170 One CAN bit time is specified as four non-overlapping time segments. Each segment is con- structed from an integer multiple of the Time Quantum. The Time Quantum or TQ is the smallest discrete timing resolution used by a CAN node. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 171 Atmel ATmega16/32/64/M1/C1 Figure 16-3. CAN Bit Construction CAN Frame (producer) Transmission Point (producer) Nominal CAN Bit Time Time Quantum (producer) Segments SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 (producer) propagation delay Segments SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 (consumer) Sample Point 16.2.3.2 Synchronization Segment The first segment is used to synchronize the various bus nodes.
Page 172 It is the time required for the logic to determine the bit level of a sampled bit. The IPT begins at the sample point, is measured in TQ and is fixed at 2TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, PS2 minimum shall not be less than the IPT.
Page 173 Atmel ATmega16/32/64/M1/C1 The bus access conflict is resolved during the arbitration field mostly over the identifier value. If a data frame and a remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote frame (c.f. RTR bit).
Page 174: Can Controller
In this way, the CPU load is strongly reduced compared to a basic-CAN solution. Using full-CAN controller, high baudrates and high bus loads with many messages can be handled. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 175: Can Channel
Atmel ATmega16/32/64/M1/C1 Figure 16-5. CAN Controller Structure Low priority Control Status IDtag+IDmask Buffer MOb i Time Stamp MOb i Scanning Control Status IDtag+IDmask Buffer MOb2 Gen. Control Time Stamp Gen. Status Enable MOb Internal Interrupt TxCAN MOb2 Internal Bit Timing...
Page 176 The total number of TQ in a bit time has to be programmed at least from 8 to 25. Figure 16-7. Sample and Transmission Point Bit Timing PRS (3-bit length) Sample PHS1 (3-bit length) Point Fcan (Tscl) Prescaler BRP Time Quantum Transmission PHS2 (3-bit length) Point SJW (2-bit length) Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 177 Atmel ATmega16/32/64/M1/C1 Figure 16-8. General Structure of a Bit Period Bit Rate Prescaler Tscl (TQ) one nominal bit Data Tsyns(5) Tprs Tphs1 Tphs2 Notes: 1. Phase error < 0 2. Phase error > 0 Tphs1+Tsjw Tphs2+Tsjw 3. Phase error > 0 4.
Page 178: Message Objects
RTR Tag Operating Mode Disabled Tx Data Frame Tx Remote Frame Rx Data Frame Rx Remote Frame Rx Remote Frame then, Tx Data Frame (reply) Frame Buffer Receive Mode 16.5.2.1 Disabled In this mode, the MOb is “free”. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 179 Atmel ATmega16/32/64/M1/C1 16.5.2.2 Tx Data & Remote Frame 1. Several fields must be initialized before sending: – Identifier tag (IDT) – Identifier extension (IDE) – Remote transmission request (RTRTAG) – Data length code (DLC) – Reserved bit(s) tag (RBnTAG) – Data bytes of message (MSG) 2.
Page 180 Upon a reception hit (i.e., a good comparison between the ID + RTR + RBn + IDE received and an IDT+ RTRTAG + RBnTAG + IDE specified while taking the comparison mask into account) the IDT + RTRTAG + RBnTAG + IDE received are updated in the MOb (written over the registers). Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 181 Atmel ATmega16/32/64/M1/C1 Figure 16-10. Acceptance Filter Block Diagram internal RxDcan Rx Shift Register (internal) ID & RB 14(33) RB excluded Hit MOb[i] 13(31) Write Enable 14(33) 13(31) - RB excluded 13(31) ID & RB RTRTAG IDMSK RTRMSK IDEMSK CANIDT Registers & CANCDMOB (MOb[i])
Page 182: Can Timer
16.6.4 Stamping Message The capture of the timer value is done in the MOb which receives or sends the frame. All man- aged MOb are stamped, the stamping of a received (sent) frame occurs on RxOk (TXOK). Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 183: Error Management
Atmel ATmega16/32/64/M1/C1 16.7 Error Management 16.7.1 Fault Confinement The CAN channel may be in one of the three following states: • Error active (default): The CAN channel takes part in bus communication and can send an active error frame when the CAN macro detects an error.
Page 184: Interrupts
• Interrupt on frame buffer full, • Interrupt on “Bus Off” setting, • Interrupt on overrun of CAN timer. The general interrupt enable is provided by ENIT bit and the specific interrupt enable for CAN timer overrun is provided by ENORVT bit. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 185 Atmel ATmega16/32/64/M1/C1 Figure 16-14. CAN Controller Interrupt Structure CANGIE.4 CANGIE.5 CANGIE.3 ENTX ENRX ENERR CANSIT 1/2 SIT[i] CANSTMOB.6 TXOK[i] CANIE 1/2 CANSTMOB.5 RXOK[i] IEMOB[i] CANSTMOB.4 BERR[i] CANSTMOB.3 SERR[i] CANGIT.7 CANSTMOB.2 CERR[i] CANIT CANSTMOB.1 FERR[i] CANGIE.7 CANGIE.2 CANGIE.1 CANGIE.6 CANSTMOB.0 AERR[i]...
Page 186: Can Register Description
0 ID Mask 1 MOb0 - ID Mask 1 Time Stamp Low MOb0 - Time Stamp Low Time Stamp High MOb0 - Time Stamp High Message Data MOb0 - Mess. Data - byte 0 8 bytes Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 187: General Can Registers
Atmel ATmega16/32/64/M1/C1 16.10 General CAN Registers 16.10.1 CAN General Control Register - CANGCON ABRQ OVRQ SYNTTC LISTEN TEST ENA/STB SWRES CANGCON Read/Write Initial Value • Bit 7 – ABRQ: Abort Request This is not an auto resettable bit. – 0 - no request.
Page 188 • Bit 3 – RXBSY: Receiver Busy This flag does not generate an interrupt. – 0 - receiver not busy – 1 - receiver busy: set by hardware as long as a frame is received or monitored. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 189 Atmel ATmega16/32/64/M1/C1 • Bit 2 – ENFG: Enable Flag This flag does not generate an interrupt. – 0 - CAN controller disable: because an enable/standby command is not immediately effective, this status gives the true state of the chosen mode.
Page 190 – 0 - interrupt disabled. – 1- CANIT interrupt enabled. • Bit 6 – ENBOFF: Enable Bus Off Interrupt – 0 - interrupt disabled. – 1- bus off interrupt enabled. • Bit 5 – ENRX: Enable Receive Interrupt Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 191 Atmel ATmega16/32/64/M1/C1 – 0 - interrupt disabled. – 1- receive interrupt enabled. • Bit 4 – ENTX: Enable Transmit Interrupt – 0 - interrupt disabled. – 1- transmit interrupt enabled. • Bit 3 – ENERR: Enable MOb Errors Interrupt – 0 - interrupt disabled.
Page 192 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CANBT1 Read/Write Initial Value • Bit 7– Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT1 is written. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 193 Atmel ATmega16/32/64/M1/C1 • Bit 6:1 – BRP5:0: Baud Rate Prescaler The period of the CAN controller system clock Tscl is programmable and determines the individ- ual bit timing. BRP[5:0] Tscl -------------------------------------- - frequency If ‘BRP[5..0]=0’, see Section 16.4.3 “Baud Rate” on page 177 Section •...
Page 194 • Bit 7:0 – TPRSC7:0: CAN Timer Prescaler Prescaler for the CAN timer upper counter range 0 to 255. It provides the clock to the CAN timer if the CAN controller is enabled. x 8 x (CANTCON [7:0] + 1) CANTIM Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 195 Atmel ATmega16/32/64/M1/C1 16.10.12 CAN Timer Registers - CANTIML and CANTIMH CANTIM7 CANTIM6 CANTIM5 CANTIM4 CANTIM3 CANTIM2 CANTIM1 CANTIM0 CANTIML CANTIM15 CANTIM14 CANTIM13 CANTIM12 CANTIM11 CANTIM10 CANTIM9 CANTIM8 CANTIMH Read/Write Initial Value • Bits 15:0 - CANTIM15:0: CAN Timer Count CAN timer counter range 0 to 65,535.
Page 196: Mob Registers
The communication enabled by reception is completed. RxOK rises at the end of the 6 bit of EOF field. In case of two or more message object reception hits, the lower MOb index (0 to 14) is updated first. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 197 Atmel ATmega16/32/64/M1/C1 • Bit 4 – BERR: Bit Error (Only in Transmission) This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. The bit value monitored is different from the bit value sent.
Page 198 IDT11 IDT10 IDT9 IDT8 IDT7 IDT6 IDT5 CANIDT3 IDT20 IDT19 IDT18 IDT17 IDT16 IDT15 IDT14 IDT13 CANIDT2 IDT28 IDT27 IDT26 IDT25 IDT24 IDT23 IDT22 IDT21 CANIDT1 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 Read/Write Initial Value Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 199 Atmel ATmega16/32/64/M1/C1 V2.0 part A • Bit 31:21 – IDT10:0: Identifier Tag Identifier field of the remote or data frame to send. This field is updated with the corresponding value of the remote or data frame received. • Bit 20:3 – Reserved Bits These bits are reserved for future use.
Page 200 – 1 - bit comparison enabled. V2.0 part B • Bit 31:3 – IDMSK28:0: Identifier Mask – 0 - comparison true forced - See “Acceptance Filter” on page 180. – 1 - bit comparison enabled. - See “Acceptance Filter” on page 180. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 201 Atmel ATmega16/32/64/M1/C1 • Bit 2 – RTRMSK: Remote Transmission Request Mask – 0 - comparison true forced – 1 - bit comparison enabled. • Bit 1 – Reserved Bit Writing zero in this bit is recommended. • Bit 0 – IDEMSK: Identifier Extension Mask –...
Page 202: Examples Of Can Baud Rate Setting
75 % 0.500 0x0A 0x04 0x13 12.000 0.250 0x04 0x0E 0x4B 75 % 0.416666 0x08 0x08 0x25 0.500 0x0A 0x0C 0x37 75 % 1.000 0x16 0x04 0x13 0.500 0x0A 0x0E 0x4B 75 % 0.833333 0x12 0x08 0x25 Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 203 Atmel ATmega16/32/64/M1/C1 Table 16-2. Examples of CAN Baud Rate Settings for Commonly Frequencies (Continued) Description Segments Registers Rate Sampling Tbit Tprs Tph1 Tph2 Tsjw (MHz) (Kbps) Point (µs) (TQ) (TQ) (TQ) (TQ) (TQ) CANBT1 CANBT2 CANBT3 - - - n o...
Page 204: Lin / Uart - Local Interconnect Network Controller Or Uart
Full Duplex Operation (Independent Serial Receive and Transmit Processes) • Asynchronous Operation • High Resolution Baud Rate Generator • Hardware Support of 8 Data Bits, Odd/Even/No Parity Bit, 1 Stop Bit Frames • Data Over-Run and Framing Error Detection Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 205: Lin Protocol
Atmel ATmega16/32/64/M1/C1 17.3 LIN Protocol 17.3.1 Master and Slave A LIN cluster consists of one master task and several slave tasks. A master node contains the master task as well as a slave task. All other nodes contain a slave task only.
Page 206: Lin / Uart Controller
• Rx LIN Header function, • LIN Response function. These functions mainly use two services: • Rx service, • Tx service. Because these two services are basically UART services, the controller is also able to switch into an UART function. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 207 Atmel ATmega16/32/64/M1/C1 17.4.1 LIN Overview The LIN/UART controller is designed to match as closely as possible to the LIN software appli- cation structure. The LIN software application is developed as independent tasks, several slave tasks and one master task (c.f.
Page 208 Synchronization Monitoring Data FIFO BUFFER 17.4.4 LIN/UART Command Overview Figure 17-5. LIN/UART Command Dependencies Response Tx Header IDOK TXOK Response Rx Header RXOK LIN Abort Automatic Return Recommended DISABLE UART Possible Byte Transfer Byte Full Duplex Byte Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 209 Atmel ATmega16/32/64/M1/C1 Table 17-1. LIN/UART Command List LCMD[2 LCMD[1 LCMD[0 LENA Command Comment Disable peripheral Rx Header - LIN abort LIN withdrawal Tx Header LCMD[2..0]=000 after Tx Rx Response LCMD[2..0]=000 after Rx Tx Response LCMD[2..0]=000 after Tx Byte transfer no CRC, no Time out...
Page 210 While the controller is sending or receiving a response, BREAK and SYNCH fields can be detected and the identifier of this new header will be recorded. Of course, specific errors on the previous response will be maintained with this identifier reception. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 211 Atmel ATmega16/32/64/M1/C1 17.4.6.4 Handling Data of LIN response A FIFO data buffer is used for data of the LIN response. After setting all parameters in the LIN- SEL register, repeated accesses to the LINDAT register perform data read or data write (c.f.
Page 212: Lin / Uart Description
• LIN13 = 1: LIN 1.3 protocol. The controller checks the LIN13 bit in computing the checksum (enhanced checksum in LIN2.1 / classic checksum in LIN 1.3). See “Rx & TX Response Functions” on page 210. This bit is irrelevant for UART commands. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 213 Atmel ATmega16/32/64/M1/C1 17.5.4 Configuration Depending on the mode (LIN or UART), LCONF[1..0] bits of the LINCR register set the controller in the following configuration (Table 17-3): Table 17-3. Configuration Table versus Mode Mode LCONF[1..0] Configuration LIN standard configuration (default) No CRC field detection or transmission...
Page 214 Equation for calculating baud rate: BAUD = / LBT[5..0] x (LDIV[11..0] + 1) Equation for setting LINDIV value: LDIV[11..0] = ( / LBT[5..0] x BAUD ) - 1 Note that in reception a majority vote on three samplings is made. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 215 Atmel ATmega16/32/64/M1/C1 17.5.6.2 Re-synchronization in LIN Mode When waiting for Rx Header, LBT[5..0] = 32 in LINBTR register. The re-synchronization begins when the BREAK is detected. If the BREAK size is not in the range (11 bits min., 28 bits max. —...
Page 216 • If an error occurs, Rx stops, the corresponding error flag is set and LTXDL will give the number of received bytes without error, • If no error occurs, LRXOK is set after the reception of the CHECKSUM, LRXDL will be unchanged (and LTXDL = LRXDL). Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 217 Atmel ATmega16/32/64/M1/C1 17.5.7.4 Data Length in Tx Response Figure 17-10. LIN1.3 - Tx Response - No error LIDOK LTXOK Byte Byte Byte Byte DATA-0 DATA-1 DATA-2 DATA-3 CHECKSUM LIN bus LRXDL (*) LTXDL (*) LBUSY LCMD2..0=000 LCMD=Tx Response (*) : LRXDL & LTXDL updated by Rx Response or Tx Response task •...
Page 218 SYNCH and Frame_Maximum IDENTIFIER fields (see Section 17.5.10 “Frame Time Out” on page 219). • LOVERR = LIN OVerrun ERRor. Overrun error will be flagged if a new command (other than LIN Abort) is entered while ‘Busy Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 219 Atmel ATmega16/32/64/M1/C1 signal’ is present. In UART mode, an overrun error will be flagged if a received byte overwrites the byte stored in the serial input buffer. • LABORT LIN abort transfer reflects a previous LIN Abort command (LCMD[2..0] = 000) while ‘Busy signal’...
Page 220 221, the four communication flags of the LINSIR register are combined to drive two interrupts. Each of these flags have their respective enable interrupt bit in LINENIR register. (see Section 17.5.8 “xxOK Flags” on page 218 Section 17.5.9 “xxERR Flags” on page 218). Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 221 Atmel ATmega16/32/64/M1/C1 Figure 17-13. LIN Interrupt Mapping LINERR.7 LABORT LINERR.6 LTOERR LINERR.5 LOVERR LINERR.4 LINSIR.3 LFERR LIN ERR LERR LINERR.3 LSERR LINENIR.3 LINENIR.2 LINENIR.1 LINENIR.0 LINERR.2 LPERR LENERR LENIDOK LENTXOK LENRXOK LINERR.1 LINSIR.2 LCERR LIDOK LINERR.0 LINSIR.1 LBERR LIN IT LTXOK LINSIR.0...
Page 222 - Note that LAINC has no more effect on the auto-incrementation and the access to the full FIFO is done setting LINDX[2..0] of LINSEL. Note: When a debugger break occurs, the state machine of the LIN/UART controller is stopped (included frame time-out) and further communication may be corrupted. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 223: Lin / Uart Register Description
Atmel ATmega16/32/64/M1/C1 17.6 LIN / UART Register Description Table 17-5. LIN/UART Register Bits Summary Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSWRES LIN13 LCONF1 LCONF0 LENA LCMD2 LCMD1 LCMD0 LINCR...
Page 224 – 101 = Identifier 61 (0x3D), – 110 = Identifier 62 (0x3E), – 111 = Identifier 63 (0x3F). • Bit 4 - LBUSY: Busy Signal – 0 = Not busy, – 1 = Busy (receiving or transmitting). Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 225 Atmel ATmega16/32/64/M1/C1 • Bit 3 - LERR: Error Interrupt It is a logical OR of LINERR register bits. This bit generates an interrupt if its respective enable bit - LENERR - is set in LINENIR. – 0 = No error, –...
Page 226 • Bit 3 - LSERR: Synchronization Error Flag – 0 = No error, – 1 = Synchronization error. This bit is cleared when LERR bit in LINSIR is cleared. • Bit 2 - LPERR: Parity Error Flag – 0 = No error, Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 227 Atmel ATmega16/32/64/M1/C1 – 1 = Parity error. This bit is cleared when LERR bit in LINSIR is cleared. • Bit 1 - LCERR: Checksum Error Flag – 0 = No error, – 1 = Checksum error. This bit is cleared when LERR bit in LINSIR is cleared.
Page 228 In LIN 1.3 mode: 4-bit identifier. In UART mode this field is unused. • Bits 5:0 - LID[5:0]: LIN 2.1 Identifier In LIN 2.1 mode: 6-bit identifier (no length transported). In UART mode this field is unused. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 229 Atmel ATmega16/32/64/M1/C1 17.6.9 LIN Data Buffer Selection Register - LINSEL LAINC LINDX2 LINDX1 LINDX0 LINSEL Read/Write Initial Value • Bits 7:4 - Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written to zero when LINSEL is written.
Page 230: Analog To Digital Converter - Adc
On-chip. The voltage refer- ence may be externally decoupled at the AREF pin by a capacitor (e.g., 10 nF) for better noise performance. In any case this capacitor shout not be greater than 10% of the AVCC smoothing capacitor. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 231 Atmel ATmega16/32/64/M1/C1 Figure 18-1. Analog to Digital Converter Block Schematic Current Source ISRCEN AREF / ISRC ISRC AREFEN AVCC Internal 2.56V Reference REFS0 REFS1 ADC0 ADC1 ADC2 ADC3 ADC4 Coarse/Fine DAC ADC5 AMP2-/ADC6 ADC7 ADCH AMP1-/ADC8 AMP1+/ADC9 ADCL ADC10 AMP0-...
Page 232: Operation
Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 233: Prescaling And Conversion Timing
Atmel ATmega16/32/64/M1/C1 Figure 18-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF ADATE SOURCE 1 CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished.
Page 234 Figure 18-5. ADC Timing Diagram, Single Conversion One Conversion Next Conversion Cycle Number ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion MUX and REFS MUX and REFS Complete Update Update Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 235: Changing Channel Or Reference Selection
Atmel ATmega16/32/64/M1/C1 Figure 18-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion Next Conversion Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Prescaler Conversion Prescaler Hold Reset Complete...
Page 236 When The ADC and COMPARATOR share the same channel (Possible configuration for AMP1+, AMP1- and AMP2-), up to revision B of ATmega32M1 the comparator is disconnected during the sampling of the ADC. For ATmega16/64 and ATmega32 revision C, the COMPARATOR is always connected.
Page 237: Adc Noise Canceler
Atmel ATmega16/32/64/M1/C1 If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may switch between AV and 2.56V as...
Page 238 (LSBs). The lowest code is read as 0, and the highest code is read as 2 Several parameters describe the deviation from the ideal behavior: • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 239 Atmel ATmega16/32/64/M1/C1 Figure 18-9. Offset Error Output Code Ideal ADC Actual ADC Offset Error Input Voltage • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).
Page 240 • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 241: Adc Conversion Result
Atmel ATmega16/32/64/M1/C1 18.7 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is: ⋅ 1023 ---------------------------- - where V...
Page 242 – ADCR = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029. – ADCL will thus read 0x40, and ADCH will read 0x0A. Writing zero to ADLAR right adjusts the result: ADCL = 0x00, ADCH = 0x29. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 243: Temperature Measurement
Atmel ATmega16/32/64/M1/C1 18.8 Temperature Measurement The temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended ADC input. MUX[4..0] bits in ADMUX register enables the temperature sensor. The internal 2.56V voltage reference must also be selected for the ADC voltage reference source in the temperature sensor measurement.
Page 244 TS_Offset is the signed twos complement 7-bit temperature sensor offset reading stored as pre- viously in the signature row at address 0x0005. See section 24.7.10 in the ATmega32M1 Automotive datasheet for details of reading the Signa- ture Row. Atmel ATmega16/32/64/M1/C1...
Page 245: Adc Register Description
Atmel ATmega16/32/64/M1/C1 18.9 ADC Register Description The ADC of the ATmega16/32/64/M1/C1 is controlled through 3 different registers. The ADC- SRA and The ADCSRB registers which are the ADC Control and Status registers, and the ADMUX which allows to select the Vref source and the channel to be converted.
Page 246 • Bit 7 – ADEN: ADC Enable Bit Set this bit to enable the ADC. Clear this bit to disable the ADC. Clearing this bit while a conversion is running will take effect at the end of the conversion. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 247 Atmel ATmega16/32/64/M1/C1 • Bit 6– ADSC: ADC Start Conversion Bit Set this bit to start a conversion in single conversion mode or to start the first conversion in free running mode. Cleared by hardware when the conversion is complete. Writing this bit to zero has no effect.
Page 248 Timer/Counter1 Compare Match B Timer/Counter1 Overflow Timer/Counter1 Capture Event PSC Module 0 Synchronization Signal PSC Module 1 Synchronization Signal PSC Module 2 Synchronization Signal Analog comparator 0 Analog comparator 1 Analog comparator 2 Analog comparator 3 Reserved Reserved Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 249 Atmel ATmega16/32/64/M1/C1 18.9.4 ADC Result Data Registers – ADCH and ADCL When an ADC conversion is complete, the conversion results are stored in these two result data registers. When the ADCL register is read, the two ADC result data registers can’t be updated until the ADCH register has also been read.
Page 250: Amplifier
Until the conversion is not achieved, it is not possible to start a conversion on another channel. In order to have a better understanding of the functioning of the amplifier synchronization, two timing diagram examples are shown Figure 18-15 Figure 18-16. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 251 Atmel ATmega16/32/64/M1/C1 As soon as a conversion is requested thanks to the ADSC bit, the Analog to Digital Conversion is started. In case the amplifier output is modified during the sample phase of the ADC, the on-going conversion is aborted and restarted as soon as the output of the amplifier is stable.
Page 252 ADTS bits in the ADCSRB register. In auto trigger conversion, the free running mode is not possible unless the ADSC bit in ADCSRA is set by soft after each conversion. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 253 Atmel ATmega16/32/64/M1/C1 The block diagram of the two amplifiers is shown on Figure 18-17. Figure 18-17. Amplifiers block diagram AMP0+ Toward ADC MUX (AMP0) AMP0- ADCK/8 Timer 0 Compare Match Timer 0 Overflow Timer 1 Compare Match Timer 1 Overflow...
Page 254: Amplifier Control Registers
• Bit 2:0 – AMP0TS2,AMP0TS1,AMP0TS0: Amplifier 0 Clock Source Selection Bits In accordance with the Table 18-9, these 3 bits select the event which will generate the clock for the amplifier 0. This clock source is necessary to start the conversion on the amplified channel. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 255 Atmel ATmega16/32/64/M1/C1 Table 18-9. AMP0 Clock Source Selection AMP0TS2 AMP0TS1 AMP0TS0 Clock Source ADC Clock/8 Timer/Counter0 Compare Match Timer/Counter0 Overflow Timer/Counter1 Compare Match B Timer/Counter1 Overflow PSC Module 0 Synchronization Signal (PSS0) PSC Module 1 Synchronization Signal (PSS1) PSC Module 2 Synchronization Signal (PSS2) 18.11.2...
Page 256 Clear this bit to normally use the Amplifier 2. • Bit 5, 4 – AMP2G1, 0: Amplifier 2 Gain Selection Bits These 2 bits determine the gain of the amplifier 2. The different setting are shown in Table 18-12. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 257 Atmel ATmega16/32/64/M1/C1 Table 18-12. Amplifier 2 Gain Selection AMP2G1 AMP2G0 Description Gain 5 Gain 10 Gain 20 Gain 40 To ensure an accurate result, after the gain value has been changed, the amplifier input needs to have a quite stable input value during at least 4 Amplifier synchronization clock periods.
Page 258: Isrc - Current Source
When ISRCEN bit is set, the ISRC pin sources 100µA. Otherwise this pin keeps its initial function. Figure 19-1. Current Source Block Diagram AVCC 100 uA ISRCEN AREF / ISRC AREF Internal Circuit AREFEN External Resistor ADC Input Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 259: Typical Applications
Atmel ATmega16/32/64/M1/C1 19.2 Typical applications 19.2.1 LIN Current Source During the configuration of a LIN node in a cluster, it may be necessary to attribute dynamically an unique physical address to every cluster node. The way to do it is not described in the LIN protocol.
Page 260 An external resistor used in conjunction with the Current Source can be used as voltage refer- ence for external devices. Using a resistor in serie with a lower tolerance than the Current Source accuracy (≤ 2%) is recommended. Table 19-2 gives an example of voltage references using standard values of resistors. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 261: Control Register
Atmel ATmega16/32/64/M1/C1 19.2.4 Threshold Reference for Internal Analog Comparator An external resistor used in conjunction with the Current Source can be used as threshold refer- ence for internal Analog Comparator (See ”Analog Comparator” on page 262.). This can be connected to AIN0 (negative Analog Compare input pin) as well as AIN1 (positive Analog Com- pare input pin).
Page 262: Analog Comparator
The interrupt flags can also be used to synchronize ADC or DAC conversions. Moreover, the comparator’s output of the comparator 1 can be set to trigger the Timer/Counter1 Input Capture function. A block diagram of the four comparators and their surrounding logic is shown in Figure 20-1. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 263: Use Of Adc Amplifiers
Atmel ATmega16/32/64/M1/C1 (1)(2) Figure 20-1. Analog Comparator Block Diagram AC0O (/2) AC0IF ACMP0 Interrupt Sensitivity Control Analog Comparator 0 Interrupt ACMPN0 AMP0 AC0IE AC0EN AC0IS1 AC0IS0 AMPCMP0 AMPCMP0 AC1O (/2) AC0M 2 1 0 AC1IF ACMP1 Interrupt Sensitivity Control Analog Comparator 1 Interrupt...
Page 264: Analog Comparator Register Description
• Bit 2, 1, 0– AC0M2, AC0M1, AC0M0: Analog Comparator 0 Multiplexer register These 3 bits determine the input of the negative input of the analog comparator. The different setting are shown in Table 20-2. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 265 Atmel ATmega16/32/64/M1/C1 Table 20-2. Analog Comparator 0 negative input selection AC0M2 AC0M1 AC0M0 Description “Vref”/6.40 “Vref”/3.20 “Vref”/2.13 “Vref”/1.60 Bandgap (1.1V) DAC result Analog Comparator Negative Input (ACMPM pin) Reserved 20.4.2 Analog Comparator 1Control Register – AC1CON AC1EN AC1IE AC1IS1 AC1IS0...
Page 266 Comparator Interrupt on output toggle Reserved Comparator interrupt on output falling edge Comparator interrupt on output rising edge Bit 3 – Res: Reserved Bit This bit is an unused bit in the ATmega16/32/64/M1/C1, and will always read as zero. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 267 Atmel ATmega16/32/64/M1/C1 • Bit 2, 1, 0– AC2M2, AC2M1, AC2M0: Analog Comparator 2 Multiplexer register These 3 bits determine the input of the negative input of the analog comparator. The different setting are shown in Table 20-6. Table 20-6. Analog Comparator 2 negative input selection...
Page 268 AC0IE in AC0CON register is set. Anyway, this bit is cleared by writing a logical one on it. This bit can also be used to synchronize ADC or DAC conversions. • Bit 3– AC3O: Analog Comparator 3 Output Bit Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 269 Atmel ATmega16/32/64/M1/C1 AC3O bit is directly the output of the Analog comparator 2. Set when the output of the comparator is high. Cleared when the output comparator is low. • Bit 2– AC2O: Analog Comparator 2 Output Bit AC2O bit is directly the output of the Analog comparator 2.
Page 270: Digital To Analog Converter - Dac
The reference voltage is the same as the one used for the ADC, See “Clock Prescaler Register – CLKPR” on page 38.. These nominally 2.56V Vref or AV are provided On-chip. The voltage reference may be externally decoupled at the AREF pin by a capacitor for better noise performance. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 271: Operation
Atmel ATmega16/32/64/M1/C1 Figure 21-1. Digital to Analog Converter Block Schematic Result D2A pin VRef Output Driver DAC High bits DAC Low bits DACH DACL Update DAC Trigger Edge Detector DAATE DATS2 DATS1 DATS0 DALA DAOE DAEN DACON 21.2 Operation The Digital to Analog Converter generates an analog signal proportional to the value of the DAC registers value.
Page 272: Dac Register Description
Clear it to automatically update the DAC input when a value is written on DACH register. Bit 6:4 – DATS2, DATS1, DATS0: DAC Trigger Selection bits These bits are only necessary in case the DAC works in auto trigger mode. It means if DAATE bit is set. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 273 Atmel ATmega16/32/64/M1/C1 In accordance with the Table 18-7, these 3 bits select the interrupt event which will generate the update of the DAC input values. The update will be generated by the rising edge of the selected interrupt flag whether the interrupt is enabled or not.
Page 274 DAC output until the DACH register has also been updated. So, to work with 10 bits, DACL must be written first before DACH. To work with 8-bit configuration, writing DACH allows the update of the DAC. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 275: Analog Feature Considerations
Atmel ATmega16/32/64/M1/C1 22. Analog Feature Considerations 22.1 Purpose The ATmega16/32/64/M1/C1 features several analog features such as ADC, DAC, Amplifiers, Comparators... The purpose of this section is to describe the interaction between these features. This section explains how to set the specific registers to get the system running.
Page 276: Analog Peripheral Clock Sources
250kHz for the amplifier when the ADC clock is 2MHz. When the ADC is clocked with a frequency higher than 2MHz the amplifier cannot be clocked by the ADC clock. See “Amplifier” on page 250. for a complete description of the Amplifier clock system. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 277: Debugwire On-Chip Debug System
Atmel ATmega16/32/64/M1/C1 23. debugWIRE On-chip Debug System 23.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs) •...
Page 278: Software Break Points
The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 279: Boot Loader Support - Read-While-Write Self-Programming Atmega16/32/64/M1/C1
Atmel ATmega16/32/64/M1/C1 24. Boot Loader Support – Read-While-Write Self-Programming ATmega16/32/64/M1/C1 In ATmega16/32/64/M1/C1, the Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
Page 280: Read-While-Write And No Read-While-Write Flash Sections
Page Erase or Page Write operation. Table 24-1. Read-While-Write Features Which Section does the Z-pointer Which Section Can Address During the be Read During Is the CPU Read-While-Write Programming? Programming? Halted? Supported? RWW Section NRWW Section NRWW Section None Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 281 Atmel ATmega16/32/64/M1/C1 Figure 24-1. Read-While-Write vs. No Read-While-Write Read-While-Write (RWW) Section Z-pointer Addresses NRWW Section Z-pointer Addresses RWW No Read-While-Write (NRWW) Section Section CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation...
Page 282: Boot Loader Lock Bits
The general Write Lock (Lock Bit mode 2) does not control the programming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock (Lock Bit mode 1) does not control reading nor writing by LPM/SPM, if it is attempted. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 283: Entering The Boot Loader Program
Atmel ATmega16/32/64/M1/C1 Table 24-2. Boot Lock Bit0 Protection Modes (Application Section) BLB0 Mode BLB02 BLB01 Protection No restrictions for SPM or LPM accessing the Application section. SPM is not allowed to write to the Application section. SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
Page 284 An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Reg- ister, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 288 details. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 285: Addressing The Flash During Self-Programming
Atmel ATmega16/32/64/M1/C1 • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer.
Page 286: Self-Programming The Flash
The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page. See “Simple Assembly Code Example for a Boot Loader” on page 290 for an assembly code example. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 287 Atmel ATmega16/32/64/M1/C1 24.7.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
Page 288 SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be loaded in the destination regis- Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 289 Atmel ATmega16/32/64/M1/C1 ter as shown below. Refer to Table 25-4 on page 298 for a detailed description and mapping of the Fuse Low byte. FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0 Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc- tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.
Page 290 ; loader section or that the interrupts are disabled. .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words .org SMALLBOOTSTART Write_page: ; Page Erase spmcrval, (1<<PGERS) | (1<<SPMEN) call Do_spm ; re-enable the RWW section Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 291 Atmel ATmega16/32/64/M1/C1 spmcrval, (1<<RWWSRE) | (1<<SPMEN) call Do_spm ; transfer data from RAM to Flash page buffer looplo, low(PAGESIZEB) ;init loop variable loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 Wrloop: r0, Y+ r1, Y+ spmcrval, (1<<SPMEN) call Do_spm adiw ZH:ZL, 2 sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256...
Page 292 Pages Address Read-While-Write section (RWW) 0x0000 - 0x17FF No Read-While-Write section (NRWW) 0x1800 - 0x1FFF For details about these two section, see “NRWW – No Read-While-Write Section” on page 280 “RWW – Read-While-Write Section” on page 280. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 293 Atmel ATmega16/32/64/M1/C1 Table 24-9. Explanation of Different Variables used in Figure 24-3 and the Mapping to the Z-pointer Corresponding (Note:) Variable Z-value Description Most significant bit in the Program Counter. (The Program PCMSB Counter is 13 bits PC[2:0]) Most significant bit which is used to address the words...
Page 294 1. The different BOOTSZ Fuse configurations are shown in Figure 24-2. 2. 1 word equals 2 bytes. Table 24-14. Read-While-Write Limit Section Pages Address Read-While-Write section (RWW) 0x0000 - 0x6FFF No Read-While-Write section (NRWW) 0x7000 - 0x7FFF Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 295 Atmel ATmega16/32/64/M1/C1 For details about these two section, see “NRWW – No Read-While-Write Section” on page 280 “RWW – Read-While-Write Section” on page 280. Table 24-15. Explanation of Different Variables used in Figure 24-3 and the Mapping to the Z-pointer...
Page 296: Memory Programming
The Boot Lock bits and Fuse bits are locked in both Serial and Parallel Programming mode. Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2. 2. “1” means unprogrammed, “0” means programmed Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 297: Fuse Bits
Atmel ATmega16/32/64/M1/C1 (1)(2) Table 25-3. Lock Bit Protection Modes BLB0 Mode BLB02 BLB01 No restrictions for SPM or LPM accessing the Application section. SPM is not allowed to write to the Application section. SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
Page 298: Psc Output Behavior During Reset
PSCOUT0B, PSCOUT1B and PSCOUT2B outputs when PSCRB is programmed. If PSCBRV fuse equals 0 (programmed), the PSCOUT0B, PSCOUT1B and PSCOUT2B outputs will be forced to high state. If PSCRV fuse equals 1 (unprogrammed), the PSCOUT0B, PSCOUT1B and PSCOUT2B outputs will be forced to low state. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 299 Atmel ATmega16/32/64/M1/C1 Table 25-5. PSC Output Behavior During and after Reset until POC register is written PSCRB PSCARV PSCBRV PSCOUTnA PSCOUTnB unprogrammed normal port normal port programmed unprogrammed unprogrammed forced low forced low programmed unprogrammed programmed forced low forced high...
Page 300: Signature Bytes
25.4 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space.
Page 301: Calibration Byte
Atmel ATmega16/32/64/M1/C1 For the ATmega64M1 the signature bytes are: 1. 0x000: 0x1E (indicates manufactured by Atmel). 2. 0x001: 0x96 (indicates 64KB Flash memory). 3. 0x002: 0x84 (indicates ATmega64M1 device when 0x001 is 0x96). For the ATmega32C1 the signature bytes are: 1.
Page 302 Byte Select 2 (“0” selects Low byte, “1” selects 2’nd High byte) Bi-directional Data bus (Output when OE is DATA PB[7:0] low) Table 25-9. Pin Values Used to Enter Programming Mode Symbol Value PAGEL Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 303 Atmel ATmega16/32/64/M1/C1 Table 25-10. XA1 and XA0 Coding Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS1). Load Data (High or Low data byte for Flash determined by BS1). Load Command No Action, Idle Table 25-11.
Page 304: Serial Programming Pin Mapping
EESAVE Fuse is programmed) and Flash after a Chip Erase. • Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 305 Atmel ATmega16/32/64/M1/C1 25.8.3 Chip Erase The Chip Erase will erase the Flash and EEPROM memories plus Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed.
Page 306 PCMSB PAGEMSB PROGRAM PCPAGE PCWORD COUNTER PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE PROGRAM MEMORY PAGE PCWORD[PAGEMSB:0]: PAGE INSTRUCTION WORD PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 25-12 on page 303. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 307 Atmel ATmega16/32/64/M1/C1 Figure 25-3. Programming the Flash Waveforms 0x10 ADDR. LOW DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH ADDR. HIGH DATA XTAL1 RDY/BSY RESET +12V PAGEL Note: 1. “XX” is don’t care. The letters refer to the programming description above.
Page 308 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 309 Atmel ATmega16/32/64/M1/C1 25.8.9 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to “Programming the Flash” on page 305 for details on Command and Data loading): 1. A: Load Command “0100 0000”.
Page 310 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA. 4. Set OE to “1”. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 311 Atmel ATmega16/32/64/M1/C1 25.8.14 Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on page 305 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte, 0x00.
Page 312 OLDV OE High to DATA Tri-stated OHDZ Notes: 1. t is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits WLRH commands. 2. t is valid for the Chip Erase command. WLRH_CE Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 313: Serial Downloading
Atmel ATmega16/32/64/M1/C1 25.9 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- put). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed.
Page 314 As WD_FLASH a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. See Table 25-16 for t value. WD_FLASH Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 315 Atmel ATmega16/32/64/M1/C1 25.9.3 Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written.
Page 316 = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care 25.9.4 SPI Serial Programming Characteristics For characteristics of the SPI module see “SPI Serial Programming Characteristics” on page 316. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 317: Electrical Characteristics
Atmel ATmega16/32/64/M1/C1 26. Electrical Characteristics All DC/AC characteristics contained in this datasheet are based on simulations and character- ization of similar devices in the same process and design methods. These values are preliminary representing design targets, and will be updated after characterization of actual automotive silicon data.
Page 318 3] The sum of all IOL, for ports B2 - B5, C4 - C7, D5 - D7 should not exceed 70mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 319: Clock Characteristics
Atmel ATmega16/32/64/M1/C1 4. Although each I/O port can source more than the test conditions (10mA at = 5V, 8mA at = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOH, for ports B0 - B1, C2 - C3, D4, E1 - E2 should not exceed 100mA.
Page 320: Maximum Speed Vs. V
Input Frequency PLL Factor Lock-in Time µS Note: While connected to external clock or external oscillator, PLL Input Frequency must be selected to provide outputs with frequency in accordance with driven parts of the circuit (CPU core, PSC...) Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 321: Spi Timing Characteristics
Atmel ATmega16/32/64/M1/C1 26.7 SPI Timing Characteristics Figure 26-3 Figure 26-4 for details. Table 26-4. SPI Timing Parameters Description Mode Min. Typ. Max. SCK period Master Table 15-4 SCK high/low Master 50% duty cycle Rise/Fall time Master Setup Master Hold Master...
Page 322: Adc Characteristics
ADC clock = 2 MHz = 5V, V = 2.56V -2.0 +2.5 +5.0 ADC clock = 1 MHz Offset error = 5V, V = 2.56V -2.0 +2.5 +5.0 ADC clock = 2 MHz Ref voltage 2.56 AVCC Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 323 Atmel ATmega16/32/64/M1/C1 Table 26-6. ADC Characteristics in differential mode - T = -40°C to +125°C, V = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Units Differential conversion, gain = 5x Differential conversion, gain = 10x Resolution Bits Differential conversion, gain = 20x...
Page 324: Parallel Programming Characteristics
DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) Note: 1. The timing requirements shown in Figure 25-7 (i.e., t , and t ) also apply to load- DVXH XHXL XLDX ing operation. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 325 Atmel ATmega16/32/64/M1/C1 Figure 26-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements LOAD ADDRESS READ DATA READ DATA LOAD ADDRESS (LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE) XLOL XTAL1 BVDV OLDV OHDZ DATA (High Byte)
Page 326 OLDV OE High to DATA Tri-stated OHDZ Notes: 1. t is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits WLRH commands. 2. t is valid for the Chip Erase command. WLRH_CE Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 327: Atmega16/32/64/M1/C1 Typical Characteristics
Atmel ATmega16/32/64/M1/C1 27. ATmega16/32/64/M1/C1 Typical Characteristics All DC characteristics contained in this datasheet are based on simulations and characterization of similar devices in the same process and design methods. These values are preliminary repre- senting design targets, and will be updated after characterization of actual automotive silicon data.
Page 328: Active Supply Current
27.1 Active Supply Current Figure 27-1. Active Supply Current versus Frequency (0.1 - 1.0MHz) Figure 27-2. Active Supply Current versus Frequency (1 - 24MHz) Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 329 Atmel ATmega16/32/64/M1/C1 Figure 27-3. Active Supply Current versus V (Internal RC Oscillator, 8MHz) Figure 27-4. Active Supply Current versus V (Internal PLL Oscillator, 16MHz) 7647H–AVR–03/12...
Page 330: Idle Supply Current
27.2 Idle Supply Current Figure 27-5. Idle Supply Current versus Frequency (0.1 - 1.0MHz) Figure 27-6. Idle Supply Current versus Frequency (1 - 24MHz) Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 331 Atmel ATmega16/32/64/M1/C1 Figure 27-7. IIdle Supply Current versus V (Internal RC Oscillator, 8MHz) Figure 27-8. Idle Supply Current versus V (Internal PLL Oscillator, 16MHz) 7647H–AVR–03/12...
Page 332: Power-Down Supply Current
Additional Current Consumption (Percentage) in Active and Idle Mode Typical I (µA) Percent of Added Consumption = 5.0V, 16 Mhz = 3.0V, 8 Mhz PRCAN PRPSC PRTIM1 PRTIM0 PRSPI PRLIN PRADC 27.3 Power-Down Supply Current Figure 27-9. Power-Down Supply Current versus V (Watchdog Timer Disabled) Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 333: Pin Pull-Up
Atmel ATmega16/32/64/M1/C1 Figure 27-10. Power-Down Supply Current versus V (Watchdog Timer Enabled) 27.4 Pin Pull-up Figure 27-11. I/O Pin Pull-Up Resistor Current versus Input Voltage (V = 5V) 7647H–AVR–03/12...
Page 334 Figure 27-12. I/O Pin Pull-Up Resistor Current versus Input Voltage (V = 2.7V) Figure 27-13. Reset Pull-Up Resistor Current versus Reset Pin Voltage (V = 5V) Figure 27-14. Reset Pull-Up Resistor Current versus Reset Pin Voltage (V = 2.7V) Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 335: Pin Driver Strength
Atmel ATmega16/32/64/M1/C1 27.5 Pin Driver Strength Figure 27-15. I/O Pin Output Voltage versus Source Current (V = 5V) Figure 27-16. I/O Pin Output Voltage versus Source Current (V = 3V) 7647H–AVR–03/12...
Page 336 Figure 27-17. I/O Pin Low Output Voltage versus Source Current (V = 5V) Figure 27-18. I/O Pin Low Output Voltage versus Source Current (V = 3V) Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 337: Pin Thresholds And Hysteresis
Atmel ATmega16/32/64/M1/C1 27.6 Pin Thresholds and Hysteresis Figure 27-19. I/O Pin Input Threshold Voltage versus V (VIH, I/O Pin Read As '1') Figure 27-20. I/O Pin Input Threshold Voltage versus V (VIL, I/O Pin Read As '0') 7647H–AVR–03/12...
Page 338 Figure 27-21. I/O Pin Input HysteresisVoltage versus V Figure 27-22. Reset Input Threshold Voltage versus V (VIH, Reset Pin Read As '1') Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 339 Atmel ATmega16/32/64/M1/C1 Figure 27-23. Reset Input Threshold Voltage versus V (VIL, Reset Pin Read As '0') Figure 27-24. XTAL1 Input Threshold Voltage versus V (XTAL1 Pin Read As '1') 7647H–AVR–03/12...
Page 340: Bod Thresholds And Analog Comparator Hysterisis
Figure 27-25. XTAL1 Input Threshold Voltage versus V (XTAL1 Pin Read As '0') 27.7 BOD Thresholds and Analog Comparator Hysterisis Figure 27-26. BOD Thresholds versus Temperature (BODLEVEL Is 4.3V) Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 341 Atmel ATmega16/32/64/M1/C1 Figure 27-27. BOD Thresholds versus Temperature (BODLEVEL Is 2.7V) Figure 27-28. TypicalAnalog Comparator Hysterisis Average Thresholds versus Common Mode Voltage 40.00E-3 30.00E-3 20.00E-3 10.00E-3 000.00E+0 1.35 2.75 -10.00E-3 -20.00E-3 -30.00E-3 -40.00E-3 -50.00E-3 -60.00E-3 Common voltage (v) 7647H–AVR–03/12...
Page 342: Analog Reference
27.8 Analog Reference Figure 27-29. VREF Voltage versus V Figure 27-30. VREF Voltage versus Temperature 27.9 Internal Oscillator Speed Figure 27-31. Watchdog Oscillator Frequency versus V Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 343 Atmel ATmega16/32/64/M1/C1 Figure 27-32. Calibrated 8MHz RC Oscillator Frequency verus Temperature Figure 27-33. Calibrated 8MHz RC Oscillator Frequency versus V Figure 27-34. Calibrated 8MHz RC Oscillator Frequency versus Osccal Value 7647H–AVR–03/12...
Page 344: Instruction Set Summary
(V = 0) then PC ← PC + k + 1 BRVC Branch if Overflow Flag is Cleared None if ( I = 1) then PC ← PC + k + 1 BRIE Branch if Interrupt Enabled None Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 345 Atmel ATmega16/32/64/M1/C1 Mnemonics Operands Description Operation Flags #Clocks if ( I = 0) then PC ← PC + k + 1 BRID Branch if Interrupt Disabled None BIT AND BIT-TEST INSTRUCTIONS I/O(P,b) ← 1 Set Bit in I/O Register None I/O(P,b) ←...
Page 346 None SLEEP Sleep (see specific descr. for Sleep function) None Watchdog Reset (see specific descr. for WDR/timer) None BREAK Break For On-chip Debug Only None Note: 1. These Instructions are only available in “16K and 32K parts” Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 347: Register Summary
Atmel ATmega16/32/64/M1/C1 29. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xFF) Reserved – – – – – – – – (0xFE) Reserved – – – –...
Page 348 WGM10 page 130 (0x7F) DIDR1 – AMP2PD ACMP0D AMP0PD AMP0ND ADC10D ADC9D ADC8D page 250 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D page 249 (0x7D) Reserved – – – – – – – – Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 349 Atmel ATmega16/32/64/M1/C1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 page 38 (0x7B) ADCSRB ADHSM ISRCEN AREFEN – ADTS3...
Page 350 Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations are reserved. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 351: Errata
Atmel ATmega16/32/64/M1/C1 30. Errata 30.1 Errata Summary 30.1.1 ATmega16M1/16C1/32M1/32C1 Rev. C (Mask Revision) • LIN Break Delimiter • ADC with with PSC2-synchronized • ADC amplifier measurement is unstable 30.1.2 ATmega16M1/16C1/32M1/32C1 Rev. B (Mask Revision) • The AMPCMPx bits return 0 •...
Page 352 – Once the RESPONSE is received or sent (having RxOK or TxOK as well as LERR), use the following function: void lin_wa_tail(void) LINCR = 0x00; // It is not a RESET ! LINBTR = 0x00; LINCR = (0<<LIN13)|(1<<LENA)|(0<<LCMD2)|(0<<LCMD1)|(0<<LCMD0); The time-out counter is disabled during the RESPONSE when the workaround is set. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 353 Atmel ATmega16/32/64/M1/C1 5. Wrong TSOFFSET manufacturing calibration value. Erroneous value of TSOFFSET programmed in signature byte. (TSOFFSET was introduced from REVB silicon). Problem fix / workaround To identify RevB with wrong TSOFFSET value, check device signature byte at address 0X3F if value is not 0X42 (Ascii code ‘B’) then use the following formula.
Page 354 Workaround Wait for the end of ADC conversion before any write of new channel or reference selec- tion values in ADMUX. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 355: Ordering Information
Atmel ATmega16/32/64/M1/C1 31. Ordering Information Table 31-1. ATmega16/32/64/M1/C1 Ordering Codes Memory Size Power Supply Ordering Code Package Operation Range 2.7 - 5.5V MEGA16M1-15AZ -40°C to 125°C 2.7 - 5.5V MEGA16M1-15MZ -40°C to 125°C 2.7 - 5.5V MEGA32C1-15AZ -40°C to 125°C 2.7 - 5.5V...
Page 356: Tqfp32
32.1 TQFP32 Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 357: Qfn32
Atmel ATmega16/32/64/M1/C1 32.2 QFN32 7647H–AVR–03/12...
Page 358: Datasheet Revision History For Atmega16/32/64/M1/C1
317. 6. Updated Current Source Value, Section 26.2 “DC Characteristics” on page 317. 7. Updated Table 25-12 on page 303. 8. Updated Table 25-13 on page 303. 9. Added PCICR definition “Register Summary” on page 347. Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 359 Atmel ATmega16/32/64/M1/C1 33.7 7647B 1. Give the good signature for the CAN only product See “Signature Bytes” on page 300. 2. Provide the PCICR address in the “Register Summary” on page 347 3. Locate the SIGRD bit in SPMCSR in the “Register Summary”...
Page 360: Table Of Contents
Clock Systems and their Distribution ............29 Clock Sources ....................30 Default Clock Source ..................31 Low Power Crystal Oscillator ................31 Calibrated Internal RC Oscillator ..............33 PLL .......................34 128 kHz Internal Oscillator ................36 External Clock ....................36 Clock Output Buffer ..................37 Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 361 Atmel ATmega16/32/64/M1/C1 5.10 System Clock Prescaler ................37 Power Management and Sleep Modes ..........40 Sleep Mode Control Register ...............40 Idle Mode ......................41 ADC Noise Reduction Mode .................41 Power-down Mode ..................41 Standby Mode ....................42 Power Reduction Register ................42 Minimizing Power Consumption ..............44 System Control and Reset ..............46...
Page 362 PSC Input Mode 11xb: Halt PSC and Wait for Software Action ....148 14.12 Analog Synchronization ................149 14.13 Interrupt Handling ..................149 14.14 PSC Clock Sources ..................149 14.15 Interrupts ....................150 14.16 PSC Register Definition 151 15 Serial Peripheral Interface – SPI ............158 15.1 Features .....................158 15.2 SS Pin Functionality ...................163 Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 363 Atmel ATmega16/32/64/M1/C1 15.3 Data Modes ....................166 16 Controller Area Network - CAN ............168 16.1 Features .....................168 16.2 CAN Protocol ....................168 16.3 CAN Controller ...................174 16.4 CAN Channel ....................175 16.5 Message Objects ..................178 16.6 CAN Timer ....................182 16.7 Error Management ..................183 16.8...
Page 364 Boot Loader Features .................279 24.2 Application and Boot Loader Flash Sections ..........279 24.3 Read-While-Write and No Read-While-Write Flash Sections .....280 24.4 Boot Loader Lock Bits ................282 24.5 Entering the Boot Loader Program .............283 24.6 Addressing the Flash During Self-Programming ........285 Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 365 Atmel ATmega16/32/64/M1/C1 24.7 Self-Programming the Flash ...............286 25 Memory Programming ...............296 25.1 Program And Data Memory Lock Bits ............296 25.2 Fuse Bits .....................297 25.3 PSC Output Behavior During Reset ............298 25.4 Signature Bytes ..................300 25.5 Calibration Byte ..................301 25.6 Parallel Programming Parameters, Pin Mapping, and Commands ....301 25.7...
Page 366 30 Errata ....................351 30.1 Errata Summary ..................351 31 Ordering Information .................355 32 Package Information ................355 32.1 TQFP32 ......................356 32.2 QFN32 ......................357 33 Datasheet Revision History for ATmega16/32/64/M1/C1 ....358 34 Table of Contents ................360 Atmel ATmega16/32/64/M1/C1 7647H–AVR–03/12...
Page 367 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellec- tual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS...

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Atmel ATmega32M1 Manual

Features

1 Pin Configurations

2 Overview

3 AVR CPU Core

4 Memories

5 System Clock

6 Power Management and Sleep Modes

7 System Control and Reset

8 Interrupts

9 I/O-Ports

10 External Interrupts

11 Timer/Counter0 and Timer/Counter1 Prescalers

12 8-Bit Timer/Counter0 with PWM

16 Bit Timer/Counter1 with PWM

14 Power Stage Controller - (PSC) (Only Atmega16/32/64M1)

15 Serial Peripheral Interface - SPI

16 Controller Area Network - CAN

17 LIN / UART - Local Interconnect Network Controller or UART

18 Analog to Digital Converter - ADC

19 ISRC - Current Source

20 Analog Comparator

21 Digital to Analog Converter - DAC

22 Analog Feature Considerations

23 Debugwire On-Chip Debug System

24 Boot Loader Support - Read-While-Write Self-Programming Atmega16/32/64/M1/C1

25 Memory Programming

26 Electrical Characteristics

27 Atmega16/32/64/M1/C1 Typical Characteristics

28 Instruction Set Summary

29 Register Summary

30 Errata

31 Ordering Information

32 Package Information

33 Datasheet Revision History for Atmega16/32/64/M1/C1

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