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10.2.6
Unconnected Pins
10.3
Alternate Port Functions
ATtiny13A
54
If a logic high level ("one") is present on an asynchronous external interrupt pin configured as
"Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin" while the external interrupt
is not enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned Sleep mode, as the clamping in these sleep mode produces the requested
logic change.
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even
though most of the digital inputs are disabled in the deep sleep modes as described above, float-
ing inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset. If low power consumption during reset is
important, it is recommended to use an external pull-up or pull-down. Connecting unused pins
directly to V
or GND is not recommended, since this may cause excessive currents if the pin is
CC
accidentally configured as an output.
Most port pins have alternate functions in addition to being general digital I/Os.
shows how port pin control signals from the simplified
by alternate functions.
Figure 10-5. Alternate Port Functions
Pxn
PUOExn:
Pxn PULL-UP OVERRIDE ENABLE
PUOVxn:
Pxn PULL-UP OVERRIDE VALUE
DDOExn:
Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn:
Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn:
Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn:
Pxn PORT VALUE OVERRIDE VALUE
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP:
SLEEP CONTROL
PTOExn:
Pxn, PORT TOGGLE OVERRIDE ENABLE
Note:
WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
and PUD are common to all ports. All other signals are unique for each pin.
Figure 10-2 on page 50
PUOExn
PUOVxn
1
0
DDOExn
DDOVxn
1
0
Q
D
DDxn
Q
CLR
PVOExn
RESET
PVOVxn
1
1
0
Q
D
0
PORTxn
Q
DIEOExn
CLR
DIEOVxn
RESET
1
RRx
SLEEP
0
SYNCHRONIZER
SET
D
Q
D
Q
PINxn
L
Q
Q
CLR
CLR
PUD:
PULLUP DISABLE
WDx:
WRITE DDRx
RDx:
READ DDRx
RRx:
READ PORTx REGISTER
WRx:
WRITE PORTx
RPx:
READ PORTx PIN
WPx:
WRITE PINx
clk
:
I/O CLOCK
I/O
DIxn:
DIGITAL INPUT PIN n ON PORTx
AIOxn:
ANALOG INPUT/OUTPUT PIN n ON PORTx
Figure 10-5
can be overridden
PUD
WDx
RDx
PTOExn
WPx
WRx
RPx
clk
I/O
DIxn
AIOxn
8126F–AVR–05/12
, SLEEP,
I/O
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