Block Diagram - Atmel ATmega128 Manual

Block Diagram

Figure 2. Block Diagram
VCC
GND
DATA REGISTER
PORTF
AVCC
AGND
AREF
JTAG TAP
ON-CHIP DEBUG
BOUNDARY-
SCAN
PROGRAMMING
PEN
LOGIC
USART0
DATA REGISTER
PORTE
2467S–AVR–07/09
PF0 - PF7
PORTF DRIVERS
DATA DIR. DATA REGISTER
REG. PORTF
ADC
PROGRAM STACK
COUNTER POINTER
PROGRAM
SRAM
FLASH
INSTRUCTION
GENERAL
REGISTER
PURPOSE
REGISTERS
INSTRUCTION
DECODER
CONTROL
ALU
LINES
STATUS
REGISTER
DATA DIR. DATA REGISTER
REG. PORTE PORTB
PORTE DRIVERS
PE0 - PE7
PA0 - PA7
PORTA DRIVERS
DATA DIR.
PORTA REG. PORTA
8-BIT DATA BUS
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTERS
X
INTERRUPT
Y
UNIT
Z
EEPROM
SPI
DATA DIR. DATA REGISTER
REG. PORTB
PORTB DRIVERS
PB0 - PB7
ATmega128
PC0 - PC7
PORTC DRIVERS
DATA REGISTER DATA DIR.
PORTC REG. PORTC
CALIB. OSC
OSCILLATOR
OSCILLATOR
TIMING AND
CONTROL
TWO-WIRE SERIAL
USART1
INTERFACE
DATA DIR.
PORTD REG. PORTD
PORTD DRIVERS
PD0 - PD7
DATA REG. DATA DIR.
PORTG
REG. PORTG
PORTG DRIVERS
PG0 - PG4
3