Standards; Performance - Xilinx LogiCORE IP v1.02a Product Manual

Product Specification

Standards

The I/O Bus interface provided by the I/O Module is fully compatible with the Xilinx
Dynamic Reconfiguration Port (DRP). For a detailed description of the DRP, see the 7 Series
FPGAs Configuration User Guide

Performance

The frequency and latency of the I/O Module are optimized for use together with
MicroBlaze™. This means that the frequency targets are aligned to MicroBlaze targets as
well as the access latency optimized for MicroBlaze data access.
Maximum Frequencies
The following are clock frequencies for the target families. The maximum achievable clock
frequency can vary. The maximum achievable clock frequency and all resource counts can
be affected by the used tool flow, other tool options, additional logic in the FPGA, using
different versions of Xilinx tools, and other factors.
Table 2-1: Maximum Frequencies
Architecture
Kintex™-7
Virtex®-6
Spartan®-6
Latency
Data read from I/O Module registers is available two clock cycles after the address strobe is
asserted.
I/O Module v1.02a
PG052 October 16, 2012
[Ref
Virtex-7
Artix™-7
www.xilinx.com
2].
Speed grade
-3
-3
-3
-3
-4
Chapter 2
Max Frequency
320
320
225
300
195
9
Product Specification