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XC4000E and XC4000X Series Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Low-Voltage Versions Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Additional XC4000X Series Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Taking Advantage of Reconfiguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
XC4000E and XC4000X Series Compared to the XC4000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Improvements in XC4000E and XC4000X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Additional Improvements in XC4000X Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Basic Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Configurable Logic Blocks (CLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Function Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Latches (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Clock Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Set/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Global Set/Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Data Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Using FPGA Flip-Flops and Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Using Function Generators as RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Fast Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Input/Output Blocks (IOBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
IOB Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
IOB Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Other IOB Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Three-State Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
Three-State Buffer Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
Three-State Buffer Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
Wide Edge Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
On-Chip Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
Interconnect Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
CLB Routing Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
Programmable Switch Matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Single-Length Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Double-Length Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Quad Lines (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Longlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
Direct Interconnect (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
I/O Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
Octal I/O Routing (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
Global Nets and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
Global Nets and Buffers (XC4000E only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
Global Nets and Buffers (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
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XC4000E and XC4000X Series
Table of Contents
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Table of Contents
Related Manuals for Xilinx XC4000E Series
Summary of Contents for Xilinx XC4000E Series
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Page 1: Table Of Contents
XC4000E and XC4000X Series ® Table of Contents XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E and XC4000X Series Features ..........4-5 Low-Voltage Versions Available . - Page 2 XC4000E and XC4000X Series Table of Contents Pin Descriptions ..............4-40 Boundary Scan .
- Page 3 XC4000XL CLB RAM Synchronous (Edge-Triggered) Write Timing ..... 4-76 XC4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing ... . . 4-76 XC4000XL Pin-to-Pin Output Parameter Guidelines .
- Page 4 XC4000E and XC4000X Series Table of Contents Pin Locations for XC4013E/XL Devices ......... . . 4-120 Pin Locations for XC4020E/XL Devices .
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Page 5: Xc4000E And Xc4000X Series Field Programmable Gate Arrays
• Highest Performance — 3.3 V XC4000XL XC4000X series, the XC4000XLT and XC4000XV. This • Highest Capacity — Over 180,000 Usable Gates information does not apply to the older Xilinx families: • 5V tolerant I/Os on XC4000XL XC4000, XC4000A, XC4000D, XC4000H, or XC4000L. For •... -
Page 6: Description
first be implemented in Blocks (CLBs), interconnected by a powerful hierarchy of the XC4000E or XC4000X, then migrated to one of Xilinx’ versatile routing resources, and surrounded by a perimeter compatible HardWire mask-programmed devices. -
Page 7: Xc4000E And Xc4000X Series Compared To The Xc4000
XC4000E and XC4000X Series much as 50% from XC4000 values. See “Fast Carry Logic” on page 4-18 for more information. Compared to the XC4000 Select-RAM Memory: Edge-Triggered, Synchronous For readers already familiar with the XC4000 family of Xil- RAM Modes inx Field Programmable Gate Arrays, the major new fea- tures in the XC4000 Series devices are listed in this The RAM in any CLB can be configured for synchronous,... -
Page 8: Additional Improvements In Xc4000X Only
XC4000E and XC4000X Series Field Programmable Gate Arrays Input Thresholds Additional Improvements in XC4000X Only The input thresholds of 5V devices can be globally config- Increased Routing ured for either TTL (1.2 V threshold) or CMOS (2.5 V New interconnect in the XC4000X includes twenty-two threshold), just like XC2000 and XC3000 inputs. -
Page 9: Detailed Functional Description
80 MHz and internal performance in excess XC4000X they can optionally be configured as latches. DIN of 150 MHz. Compared to older Xilinx FPGA families, can be used as a direct input to either of the two storage XC4000 Series devices are more powerful. -
Page 10: Flip-Flops
XC4000E and XC4000X Series Field Programmable Gate Arrays C 1 • • • C 4 D IN /H 2 SR/H 0 Bypass CONTROL LOGIC FUNCTION G1-G4 LOGIC FUNCTION F', G', Bypass CONTROL LOGIC FUNCTION F1-F4 (CLOCK) Multiplexer Controlled by Configuration Program X6692 Figure 2: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown) Flip-Flops... -
Page 11: Set/Reset
Set/Reset Two fast feed-through paths are available, as shown in Figure 2. A two-to-one multiplexer on each of the XQ and An asynchronous storage element input (SR) can be con- YQ outputs selects between a storage element output and figured as either set or reset. This configuration option any of the control inputs. - Page 12 The difference between level-sensitive, edge-triggered, with on-chip RAM. and dual-port RAM is only in the write operation. Read Three application notes are available from Xilinx that dis- operation and timing is identical for all modes of operation. cuss edge-triggered RAM: “ XC4000E Edge-Triggered and Dual-Port RAM Capability, ”...
- Page 13 Configuring the CLB function generators as Read/Write edge of WCLK latches the address, input data, and WE sig- memory does not affect the functionality of the other por- nals. An internal write pulse is generated that performs the tions of the CLB, with the exception of the redefinition of the write.
- Page 14 XC4000E and XC4000X Series Field Programmable Gate Arrays C 1 • • • C 4 D IN WRITE 16-LATCH DECODER ARRAY G 1 • • • G 4 1 of 16 LATCH ENABLE READ ADDRESS WRITE PULSE D IN WRITE 16-LATCH DECODER ARRAY...
- Page 15 WE pulse must be guaranteed inactive before the next rising edge of the system clock. Several F Function Generator older application notes are available from Xilinx that dis- WCLK cuss the design of level-sensitive RAMs. These application X6755 notes include XAPP031, “...
- Page 16 XC4000E and XC4000X Series Field Programmable Gate Arrays C 1 • • • C 4 WRITE 16-LATCH DECODER ARRAY 1 of 16 LATCH ENABLE READ WRITE PULSE ADDRESS G 1 • • • G 4 WRITE 16-LATCH DECODER ARRAY F 1 • • • F 4 1 of 16 LATCH ENABLE...
- Page 17 ADDRESS WRITE ENABLE DATA IN REQUIRED X6462 Figure 9: Level-Sensitive RAM Write Timing C 1 • • • C 4 D IN Enable WRITE 16-LATCH DECODER ARRAY G 1 • • • G 4 1 of 16 READ ADDRESS D IN Enable WRITE 16-LATCH...
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Page 18: Fast Carry Logic
XC4000E and XC4000X Series Field Programmable Gate Arrays C 1 • • • C 4 D 1 /A 4 D IN Enable WRITE 16-LATCH DECODER ARRAY G 1 • • • G 4 1 of 16 F 1 • • • F 4 READ ADDRESS D IN Enable... - Page 19 COUT. G4 thus becomes an additional high-speed initialization path for carry-in. The dedicated carry logic is discussed in detail in Xilinx document XAPP 013: “ Using the Dedicated Carry Logic in XC4000 .” This discussion also applies to XC4000E devices, and to XC4000X devices when the minor logic changes are taken into account.
- Page 20 XC4000E and XC4000X Series Field Programmable Gate Arrays DOWN CARRY LOGIC CARRY C OUT0 CARRY X6699 Figure 14: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000X) 4-20 March 30, 1998 (Version 1.5)
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Page 21: Input/Output Blocks (Iobs)
OUT0 FUNCTION GENERATORS IN UP X2000 IN DOWN Figure 15: Detail of XC4000E Dedicated Carry Logic Input/Output Blocks (IOBs) The choice is made by placing the appropriate library sym- bol. For example, IFD is the basic input flip-flop (rising edge User-configurable input/output blocks (IOBs) provide the triggered), and ILD is the basic input latch (transparent- interface between external package pins and the internal... - Page 22 XC4000E and XC4000X Series Field Programmable Gate Arrays Passive Slew Rate Pull-Up/ Control Pull-Down Flip-Flop Output Buffer Output Clock Flip- Input Flop/ Buffer Latch Delay Clock Enable Input Clock X6704 Figure 16: Simplified Block Diagram of XC4000E IOB Passive Slew Rate Pull-Up/ Control Pull-Down...
- Page 23 Table 9: Supported Sources for XC4000 Series Device Optional Delay Guarantees Zero Hold Time Inputs The data input to the register can optionally be delayed by several nanoseconds. With the delay enabled, the setup XC4000E/EX XC4000XL time of the input flip-flop is increased so that normal clock Series Inputs Series Inputs routing does not result in a positive hold-time requirement.
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Page 24: Iob Output Signals
GSR Figure 17 on page 4-22 also shows a two-tap delay on the input. By default, if the Fast Capture latch is used, the Xilinx Flip-Flop software assumes a Global Early buffer is driving the clock, and selects MEDDELAY to ensure a zero hold time. Select... - Page 25 This Outputs restriction is common to all high-speed digital ICs, and is not particular to Xilinx or the XC4000 Series. XC4000 Series XC4000 Series devices have a feature called “Soft Start- Outputs up,”...
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Page 26: Other Iob Options
Therefore, driven by an external source. To activate the internal pull- the Xilinx software does not move logic into the IOB func- up, attach the PULLUP library component to the net tion generators unless explicitly directed to do so. -
Page 27: Three-State Buffers
or clear on reset and after configuration. Other than the glo- Standard 3-State Buffer bal GSR net, no user-controlled set/reset signal is available All three pins are used. Place the library element BUFT. to the I/O flip-flops. The choice of set or clear applies to Connect the input to the I pin and the output to the O pin. -
Page 28: Wide Edge Decoders
XC4000E and XC4000X Series Field Programmable Gate Arrays Z = D • A + D • B + D • C + D • N ~100 kΩ BUFT BUFT BUFT BUFT X6466 "Weak Keeper" Figure 23: 3-State Buffers Implement a Multiplexer Wide Edge Decoders Dedicated decoder circuitry boosts the performance of LUP symbol. -
Page 29: Programmable Interconnect
The oscillator output is optionally available after configura- • Global routing consists of dedicated networks primarily tion. Any two of four resynchronized taps of a built-in designed to distribute clocks throughout the device with divider are also available. These taps are at the fourth, minimum delay and skew. -
Page 30: Programmable Switch Matrices
XC4000E and XC4000X Series Field Programmable Gate Arrays Quad Single Double Long Direct Connect Long Quad Long Global Long Double Single Global Carry Direct Clock Clock Chain Connect x5994 Figure 26: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only) Table 15: Routing per CLB in XC4000 Series Devices XC4000E XC4000X... - Page 31 QUAD DOUBLE SINGLE DOUBLE LONG F4 C4 G4 DIRECT FEEDBACK F2 C2 G2 LONG Common to XC4000E and XC4000X XC4000X only Programmable Switch Matrix Figure 28: Detail of Programmable Interconnect Associated with XC4000 Series CLB March 30, 1998 (Version 1.5) 4-31...
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Page 32: Double-Length Lines
XC4000E and XC4000X Series Field Programmable Gate Arrays Doubles Singles Doubles X6601 Figure 29: Single- and Double-Length Lines, with X9014 Programmable Switch Matrices (PSMs) Figure 30: Quad Lines (XC4000X only) Double-Length Lines and up to two independent outputs. Only one of the inde- pendent inputs can be buffered. -
Page 33: Direct Interconnect (Xc4000X Only)
vents undefined floating levels. However, it is overridden by I/O Routing any driver, even a pull-up resistor. XC4000 Series devices have additional routing around the Each XC4000E longline has a programmable splitter IOB ring. This routing is called a VersaRing. The VersaRing switch at its center, as does each XC4000X longline driven facilitates pin-swapping and redesign without affecting by TBUFs. - Page 34 XC4000E and XC4000X Series Field Programmable Gate Arrays Quad Single Double INTERCONNECT Long Direct Connect Long Direct Edge Double Long Global Octal Connect Decode Clock X5995 Figure 32: High-Level Routing Diagram of XC4000 Series VersaRing (Left Edge) WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC4000X only) Segment with nearest buffer connects to segment with furthest buffer X9015...
- Page 35 QUAD DOUBLE SINGLE DOUBLE LONG DIRECT LONG Common to XC4000E and XC4000X XC4000X only Figure 34: Detail of Programmable Interconnect Associated with XC4000 Series IOB (Left Edge) March 30, 1998 (Version 1.5) 4-35...
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Page 36: Global Nets And Buffers
XC4000E and XC4000X Series Field Programmable Gate Arrays IOB inputs and outputs interface with the octal lines via the Two different types of clock buffers are available in the single-length interconnect lines. Single-length lines are XC4000E: also used for communication between the octals and dou- •... - Page 37 BUFGS BUFGP PGCK1 SGCK4 PGCK4 SGCK1 BUFGS BUFGP locals locals locals locals Any BUFGS Any BUFGS locals locals One BUFGP One BUFGP per Global Line per Global Line locals locals BUFGP BUFGS PGCK2 SGCK3 SGCK2 PGCK3 BUFGP BUFGS X6604 Figure 35: XC4000E Global Net Distribution BUFGLS BUFGLS GCK1...
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Page 38: Global Nets And Buffers (Xc4000X Only)
XC4000E and XC4000X Series Field Programmable Gate Arrays Global Nets and Buffers (XC4000X only) Choosing an XC4000X Clock Buffer The clocking structure of the XC4000X provides a large Eight vertical longlines in each CLB column are driven by variety of features. However, it can be simple to use, with- special global buffers. - Page 39 X6751 X6753 Figure 38: Left and Right BUFGEs Can Drive Any or Figure 37: Any BUFGLS (GCK1 - GCK8) Can All Clock Inputs in Same Quadrant or Edge (GCK1 is Drive Any or All Clock Inputs on the Device shown. GCK2, GCK5 and GCK6 are similar.) Global Early Buffers The left-side Global Early buffers can each drive two of the Each corner of the XC4000X device has two Global Early...
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Page 40: Power Distribution
XC4000E and XC4000X Series Field Programmable Gate Arrays The top and bottom Global Early buffers are about 1 ns slower clock to out than the left and right Global Early buff- ers. Ground and Vcc Ring for The Global Early buffers can be driven by either semi-ded- I/O Drivers icated pads or internal logic. -
Page 41: Boundary Scan
Table 17: Pin Descriptions During After Pin Name Config. Config. Pin Description Permanently Dedicated Pins Eight or more (depending on package) connections to the nominal +5 V supply voltage (+3.3 V for low-voltage devices). All must be connected, and each must be decoupled with a 0.01 - 0.1 µF capacitor to Ground. -
Page 42: Configuration
XC4000E and XC4000X Series Field Programmable Gate Arrays Table 17: Pin Descriptions (Continued) During After Pin Name Config. Config. Pin Description If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs respectively. They come directly from the pads, bypassing the IOBs. These pins can also be used as inputs to the CLB logic after configuration is completed. - Page 43 Table 17: Pin Descriptions (Continued) During After Pin Name Config. Config. Pin Description A18 - A21 During Master Parallel configuration with an XC4000X master, these 4 output pins add (XC4000X 4 more bits to address the configuration EPROM. After configuration, they are user-pro- only) grammable I/O pins.