Xilinx LogiCORE IP v1.02a Product Manual page 24

.
X-Ref Target - Figure 3-1
Clk
IO_Address
IO_Byte_Enab
IO_Write_Dat
IO_Addr_Stro
IO_Read_Stro
IO_Write_Stro
IO_Read_Data
IO_Ready
X-Ref Target - Figure 3-2
Clk
IO_Address
IO_Byte_Enab
IO_Write_Dat
IO_Addr_Stro
IO_Read_Stro
IO_Write_Stro
IO_Read_Data
IO_Ready
The byte enable signals indicate which byte lanes of the data bus contain valid data. Valid
values for IO_Byte_Enable are shown in
be used instead of the two least significant bits of the IO_Address to decode byte and
halfword accesses, to ensure that byte and halfword accesses are correctly decoded
independent of MicroBlaze endianess.
Table 3-1: Valid Values for IO_Byte_Enable[3:0]
IO_Byte_Enable
[3:0]
0001
0010
0100
1000
0011
1100
1111
I/O Module v1.02a
PG052 October 16, 2012
Figure 3-1: I/O Bus Write
Figure 3-2: I/O Bus Read
Table 3-1. The IO_Byte_Enable signal should
IO_Data_Write and IO_Data_Read Byte Lanes Used
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General Design Guidelines
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