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Designing with the Core
This chapter includes guidelines and additional information to facilitate designing with the
core.
General Design Guidelines
I/O Bus
The I/O Bus provides a simple bus for accessing to external modules using MicroBlaze™
Load/Store instructions. The I/O Bus is mapped at address
C_IO_BASEADDR–C_IO_HIGHADDR in the MicroBlaze memory space, with the I/O Bus
address directly reflecting the byte address used by MicroBlaze Load/Store instructions. I/O
Bus data is 32-bit wide, with byte enables to write byte and half-word data.
The I/O Bus has a ready handshake to handle different waitstate needs, from IO_Ready
asserted the cycle after the IO_Addr_Strobe is asserted to as many cycles as needed.
There is no timeout on the I/O Bus and MicroBlaze is stalled until IO_Ready is asserted.
IO_Address, IO_Byte_Enable, IO_Write_Data, IO_Read_Strobe,
IO_Write_Strobe are only valid when IO_Addr_Strobe is asserted. For read access
IO_Read_Data is sampled at the rising Clk edge, when the slave has asserted IO_Ready.
I/O Bus read and write transactions can be found in the two following timing diagrams in
Figure 3-1
and
I/O Module v1.02a
PG052 October 16, 2012
Figure
3-2.
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