Xilinx LogiCORE IP v1.02a Product Manual page 18

Interrupt Pending Register (IRQ_PENDING)
The Interrupt Pending Register holds information on enabled interrupt events that have
occurred. IRQ_PENDING is the contents of IRQ_STATUS bit-wised masked with the
IRQ_ENABLE register. The register is read-only and the IRQ_ACK register should be used to
clear individual interrupts.
Table 2-20: Interrupt Pending Register (IRQ_PENDING)
Reserved
31 C_INTC_EXT_INTR+16 C_INTC_EXT_INTR+15
Table 2-21: Interrupt Pending Register Bit Definitions
Bit(s)
31:[C_INTC_EXT_INTR+16]
[C_INTC_EXT_INTR+15]:16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I/O Module v1.02a
PG052 October 16, 2012
INTC_Interrupt
Core Reset
Name
Access Value
- R
INTC_Interrupt R
- R
GPI4 R
GPI3 R
GPI2 R
GPI1 R
FIT4 R
FIT3 R
FIT2 R
FIT1 R
PIT4 R
PIT3 R
PIT2 R
PIT1 R
UART_RX R
UART_TX R
UART_ERR R
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Reserved
16 15
Description
Reserved
0
0 I/O Module external interrupt input signal
INTC_Interrupt [C_INTC_EXT_INTR-1:0]
mapped to corresponding bit positions in
IRQ_STATUS
0 Reserved
GPI4 changed
0
0 GPI3 changed
0 GPI2 changed
GPI1 changed
0
0 FIT4 strobe
0 FIT3 strobe
0 FIT2 strobe
FIT1 strobe
0
0 PIT4 lapsed
0 PIT3 lapsed
PIT2 lapsed
0
0 PIT1 lapsed
0 UART Received Data
0 UART Transmitted Data
UART Error
0
Register Space
Internal Interrupts
11 10 0
18
Product Specification