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Data write to I/O Module registers is performed the clock cycle after the address strobe is
asserted.
Data accesses to peripherals connected on the I/O Bus take three clock cycles plus the
number of wait states introduced by the accessed peripheral.
Throughput
The maximum throughput when using the I/O Bus is one read or write access every three
clock cycles.
Resource Utilization
Because the MicroBlaze MCS is a module that is used together with other parts of the
design in the FPGA, the utilization and timing numbers reported in this section are just
estimates, and the actual utilization of FPGA resources and timing of the MicroBlaze MCS
design will vary from the results reported here. All parameters not given in the table below
have their default values.
Table 2-2: Performance and Resource Utilization Benchmarks on Virtex-6 (xc6vlx240t-1-ff1156)
Parameter Values (other parameters at default value)
1
1
0
0
1
1
1
5
1
1
1
5
1
1
1
5
1
1
1
5
1
1
1
5
1
1
1
5
I/O Module v1.02a
PG052 October 16, 2012
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
65000
0
0
0
1
65000
1
32
0
1
65000
1
32
1
1
65000
1
32
1
www.xilinx.com
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
32
1
32
0
0
32
1
32
1
0
Resource Utilization
Device Resources
LUTs
Flip-Flops
40
75
69
110
118
173
75
122
121
216
121
280
119
361
Product Specification
10
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