Xilinx LogiCORE IP v1.02a Product Manual page 26

The UART can be configured with either fixed or programmable baud rate. When using
programmable baud rate the UART_BAUD register is used to set the baud rate. The initial
value of this register is determined from the selected fixed baud rate. The register value is
calculated by the formula:
Fixed Interval Timer, FIT
The Fixed Interval Timer generates a strobe (interrupt) signal at fixed intervals. The Fixed
Interval Timer asserts the output signal FITx_Interrupt one clock cycle every
C_FITx_NO_CLOCKS. Operation begins immediately after FPGA configuration and the clock
is running. The FITx_Toggle output signal is toggled each time FITx_Interrupt is
asserted, creating a 50% duty cycle output with twice the FITx_Interrupt period. Using the
parameter C_FITx_INTERRUPT, the FIT can be connected to the Interrupt Controller of the
I/O Module and used for generating interrupts every time the strobe occurs.
Programmable Interval Timer, PIT
The Programmable Interval Timer, PIT, has a configurable width from 1 to 32. The PIT
operation and period are controlled by software.
The PITx_Interrupt output signal is asserted one clock cycle when the timer lapses. The
timer can be used in continuous mode, where the timer reloads automatically when it
lapses. In continuous mode, the period between two PITx_Interrupt assertions is the
value in PITx Preload Register + 2 count events.
The PIT can also be used in one-shot mode, where the timer stops when it has reached zero.
The timer is implemented by means of a counter that is pre-loaded with the timer value and
then decremented. When the counter reaches zero, the timer lapses, and the interrupt
signal is generated. The timer starts counting when it is enabled by setting the EN bit in the
PITx Control Register.
The PITx_Toggle output signal is toggled each time PITx_Interrupt is asserted,
creating a 50% duty cycle output with twice the PITx_Interrupt period when the timer
is operated in continuous mode.
The value of the counter that implements the timer can be read by software if the
C_PITx_Readable parameter is enabled.The PIT can have a pre-scaler connected from any
FITx, PITx, or External. The pre-scaler is selected by the C_PITx_PRESCALER parameter. The
PIT has no pre-scaler by default. If External is selected the input signal PITx_Enable is
used as pre-scaler. Selecting External as pre-scaler can also be used to measure the width in
clock cycles of a signal connected to the PITx_Enable input.
Using the parameter C_PITx_INTERRUPT, the PIT can be connected to the Interrupt
Controller of the I/O Module and used for generating interrupts every time it lapses.
I/O Module v1.02a
PG052 October 16, 2012
Clock Frequency of Clk (Hz)
-- - -- - -- - - -- - -- - -- - -- - -- - -- - - -- - -- - -- - -- - -- - -- - -- - - -- - -- - -- - 1
UART_BAUD
=
Baud Rate 16
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General Design Guidelines
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