Xilinx LogiCORE IP v1.02a Product Manual page 20

Interrupt Acknowledge Register (IRQ_ACK)
This register is used as a command register for clearing individual interrupts in IRQ_STATUS
and IRQ_PENDING registers. All bits set to 1 clear the corresponding bits in the IRQ_STATUS
and IRQ_PENDING registers. The register is write-only.
Table 2-24: Interrupt Acknowledge Register (IRQ_ACK)
31
Table 2-25: Interrupt Acknowledge Register Bit Definitions
Bit(s) Name
31:0 IRQ_ACK
Interrupt Mode Register (IRQ_MODE)
This register is used to define which interrupts use fast interrupt mode. All bits set to 1 use
fast interrupt mode. The register is write-only. The register is only implemented when fast
interrupt mode is enabled, by setting C_INTC_HAS_FAST to 1.
Table 2-26: Interrupt Mode Register (IRQ_MODE)
31
Table 2-27: Interrupt Mode Register Bit Definitions
Bit(s) Name
31:0 IRQ_MODE
I/O Module v1.02a
PG052 October 16, 2012
Core Reset
Access Value
All bit position written with 1 will clear corresponding bits in
W 0
both the IRQ_STATUS and the IRQ_PENDING registers
IRQ_MODE
Core Reset
Access Value
W 0 All bit positions written with 1 use fast interrupt mode
www.xilinx.com
IRQ_ACK
Description
Description
Register Space
0
0
20
Product Specification