Feature Summary - Xilinx LogiCORE IP v1.02a Product Manual

X-Ref Target - Figure 1-2
Interface Controller

Feature Summary

I/O Bus
The I/O Bus provides a simple bus for accessing to external modules. The I/O Bus is mapped
in the MicroBlaze memory space, with the I/O Bus address directly reflecting the byte
address used by MicroBlaze Load/Store instructions. I/O Bus data is 32-bit wide, with byte
enables to write byte and half-word data.
The I/O Bus is fully compatible with the Xilinx Dynamic Reconfiguration Port (DRP).
UART
The Universal Asynchronous Receiver Transmitter (UART) interface provides the controller
interface for asynchronous serial data transfers. Features supported include:
• One transmit and one receive channel (full duplex)
• Configurable number of data bits in a character (5-8)
• Configurable parity bit (odd or even)
• Configurable and programmable baud rate
I/O Module v1.02a
PG052 October 16, 2012
MicroBlaze
ILMB
LMB_v10
LMB BRAM
BRAM Block
(Dual Port)
Figure 1-2: Typical MicroBlaze System
www.xilinx.com
DLMB
LMB_v10
LMB BRAM
Interface Controller
Feature Summary
I/O Module
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