Port Descriptions - Xilinx LogiCORE IP v1.02a Product Manual

Port Descriptions

The I/O ports and signals for the I/O Module are listed and described in
Table 2-3: I/O Module I/O Signals
Port Name
LMB_ABus
LMB_WriteDBus
LMB_ReadStrobe
LMB_AddrStrobe
LMB_WriteStrobe
LMB_BE
Sl_DBus
Sl_Ready
Sl_Wait
Sl_CE
Sl_UE
IO_Addr_Strobe
IO_Read_Strobe
IO_Write_Strobe
IO_Address
IO_Byte_Enable
IO_Write_Data
IO_Read_Data
IO_Ready
UART_Rx_IO
UART_Tx_IO
UART_Interrupt
(1)
FITx_Interrupt
(1)
FITx_Toggle
I/O Module v1.02a
PG052 October 16, 2012
MSB:LSB
LMB Signals
0:C_LMB_AWIDTH-1
0:C_LMB_DWIDTH-1
0:C_LMB_DWIDTH/8-1
0:C_LMB_DWIDTH-1
I/O Bus Signals
31:0
3:0
31:0
31:0
UART Signals
FIT Signals
PIT Signals
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I/O Description
I LMB Address Bus
I LMB Write Data Bus
I LMB Read Strobe
I LMB Address Strobe
I LMB Write Strobe
I LMB Byte Enable Bus
LMB Read Data Bus
O
LMB Data Ready
O
LMB Wait
O
LMB Correctable Error
O
LMB Uncorrectable Error
O
Address strobe signals valid I/O Bus output
O
signals
O I/O Bus access is a read
I/O Bus access is a write
O
Address for access
O
Byte enables for access
O
Data to write for I/O Bus write access
O
I Read data for I/O Bus read access
I Ready handshake to end I/O Bus access
Receive Data
I
Transmit Data
O
UART Interrupt
O
FITx timer lapsed
O
Inverted FITx_Toggle when FITx timer lapses
O
Port Descriptions
Table 2-3.
11
Product Specification