Lmb Timing; Clocking; Resets - Xilinx LogiCORE IP v1.02a Product Manual

An interrupt is cleared in both the Interrupt Status and Interrupt Pending Registers by
writing to the Interrupt Acknowledge Register, with bits set corresponding to the interrupts
that should be cleared.
Either normal or fast interrupt mode can be used, based on latency requirement. Fast
interrupt mode is available when the parameter C_INTC_HAS_FAST is set, and is enabled for
an interrupt by setting the corresponding bit in the Interrupt Mode Register (IRQ_MODE). In
this case, the Interrupt Controller drives the interrupt vector address of the highest priority
interrupt on the INTC_Interrupt_Address port, along with INTC_IRQ. The generated
interrupt is cleared based on acknowledge received from the processor through the
INTC_Interrupt_Ack port. The processor sends 0b01 on this port when the interrupt is
being acknowledged by the processor (that is, when branching to the interrupt service
routine), sends 0b10 when executing a return from interrupt instruction in the interrupt
service routine, and sends 0b11 when interrupts are re-enabled. The bit in IRQ_STATUS
corresponding to the interrupt is cleared when 0b10 or 0b11 is seen on the port.
With fast interrupt mode, the interrupt vector address for each interrupt is stored in the
corresponding IRQ_VECTOR register. To be compatible with normal mode, the registers are
initialized to C_INTC_BASE_VECTORS + 0x10 after reset, which is equivalent to the static
interrupt vector used by normal mode.

LMB Timing

See the MicroBlaze Bus Interfaces chapter in the MicroBlaze Processor Reference Guide
[Ref 1] for details on the transaction signaling.

Clocking

The I/O Module is fully synchronous with all clocked elements clocked with the Clk input.

Resets

The Rst input is the master reset input signal for the I/O Module.
I/O Module v1.02a
PG052 October 16, 2012
www.xilinx.com
LMB Timing
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