Xilinx LogiCORE IP v1.02a Product Manual page 14

Table 2-5: I/O Module Register Address Map (Cont'd)
Base Address + Offset (hex)
C_BASEADDR + 0x80 -
C_BASEADDR + 0xFC
(C_BASEADDR + 0x100) - C_HIGHADDR
C_IO_BASEADDR - C_IO_HIGHADDR
UART Receive Data Register (UART_RX)
This register contains data received by the UART. Reading this location results in reading the
current word from the register. When a read request is issued without having received a new
character, the previously read data is read again. This register is a read-only register. Issuing
a write request to the register does nothing but generate the write acknowledgement. The
register is implemented if C_USE_UART_RX is set to 1.
Table 2-6: UART Receive Data Register (UART_RX) (C_DATA_BITS=8)
31
Table 2-7: UART Receive Data Register Bit Definitions
Bit(s)
31:C_UART_DATA_BITS
[C_UART_DATA_BITS-1]:0
UART Transmit Data Register (UART_TX)
A register contains data to be output by the UART. Data to be transmitted is written into this
register. This is write only location. Issuing a read request to this register generates the read
acknowledgement with zero data. Writing this register when the character has not been
transmitted will overwrite previously written data, resulting in loss of data. The register is
implemented if C_USE_UART_TX is set to 1.
Table 2-8: UART Transmit Data Register (UART_TX) (C_DATA_BITS=8)
31
Table 2-9: UART Transmit Data Register Bit Definitions
Bit(s)
31:C_UART_DATA_BITS
[C_UART_DATA_BITS-1]:0
I/O Module v1.02a
PG052 October 16, 2012
Register
IRQ_VECTOR_0 -
IRQ_VECTOR_31
Reserved
I/O Bus
Reserved
Core Reset
Name
Access Value
- R 0
UART_RX R 0
Reserved
Core Reset
Name
Access Value
- R
UART_TX R
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Access
Description
Type
Interrupt Address Vector Registers
W
Mapped to I/O Bus address output
RW
IO_Address
8 7
Description
Reserved
UART Receive Data
8 7
Description
0 Reserved
0 UART Transmit Data
Register Space
UART_RX
0
UART_TX
0
14
Product Specification