Xilinx LogiCORE IP v1.02a Product Manual page 50

Table 6-1: EDK I/O Module Parameters
Parameter Name
(1)
C_FREQ
(1)
C_INSTANCE
C_BASEADDR
C_HIGHADDR
C_MASK
C_IO_HIGHADD
R
C_IO_LOWADDR
C_IO_MASK
C_LMB_AWIDTH
C_LMB_DWIDTH
1. Values automatically populated by tool.
2. The range specified by BASEADDR and HIGHADDR must comprise a complete, contiguous power-of-two range,
such that range = 2
3. The decode mask determines which bits are used by the LMB decode logic to decode a valid access to LMB.
I/O Module v1.02a
PG052 October 16, 2012
Feature/Description
Frequency of CLK input
Instance name
LMB I/O Module Register Base
Address
LMB I/O Module Register High
Address
LMB I/O Module Register Address
Space Decode Mask
LMB I/O Module I/O Bus Base
Address
LMB I/O Module I/O Bus Address
LMB I/O Module I/O Bus Address
Space Decode Mask
LMB Address Bus Width
LMB Data Bus Width
n
, and the n least significant bits of BASEADDR must be zero.
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Allowable Default
Values Value
100000000
Any legal VHDL "iomodule"
string
Valid Address 0xFFFFFFFF
(2)
Range
Valid Address 0x00000000
(2)
Range
Valid decode 0x00800000
(3)
mask
Valid Address 0xFFFFFFFF
(2)
Range
Valid Address 0x00000000
(2)
Range
Valid decode
0x00800000
(3)
mask
32
32
32 32
Parameter Values
VHDL Type
integer
string
std_logic_vector
std_logic_vector
std_logic_vector
std_logic_vector
std_logic_vector
std_logic_vector
integer
integer
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