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Table 2-5: I/O Module Register Address Map
Base Address + Offset (hex)
C_BASEADDR + 0x0
C_BASEADDR + 0x4
C_BASEADDR + 0x8
C_BASEADDR + 0xC
C_BASEADDR + 0x10
C_BASEADDR + 0x14
C_BASEADDR + 0x18
C_BASEADDR + 0x1C
C_BASEADDR + 0x20
C_BASEADDR + 0x24
C_BASEADDR + 0x28
C_BASEADDR + 0x2C
C_BASEADDR + 0x30
C_BASEADDR + 0x34
C_BASEADDR + 0x38
C_BASEADDR + 0x3C
C_BASEADDR + 0x40
C_BASEADDR + 0x44
C_BASEADDR + 0x48
C_BASEADDR + 0x4C
C_BASEADDR + 0x50
C_BASEADDR + 0x54
C_BASEADDR + 0x58
C_BASEADDR + 0x5C
C_BASEADDR + 0x60
C_BASEADDR + 0x64
C_BASEADDR + 0x68
C_BASEADDR + 0x6C
C_BASEADDR + 0x70
C_BASEADDR + 0x74
C_BASEADDR + 0x78
C_BASEADDR + 0x7C
I/O Module v1.02a
PG052 October 16, 2012
Access
Register
Type
UART_RX
R
UART_TX
W
UART_STATUS
R
IRQ_MODE
W
GPO1
W
GPO2
W
GPO3
W
GPO4
W
GPI1
R
GPI2
R
GPI3
R
GPI4
R
IRQ_STATUS
R
IRQ_PENDING
R
IRQ_ENABLE
W
IRQ_ACK
W
PIT1_PRELOAD
W
PIT1_COUNTER
R
PIT1_CONTROL
W
UART_BAUD
W
PIT2_PRELOAD
W
PIT2_COUNTER
R
PIT2_CONTROL
W
Reserved
PIT3_PRELOAD
W
PIT3_COUNTER
R
PIT3_CONTROL
W
Reserved
PIT4_PRELOAD
W
PIT4_COUNTER
R
PIT4_CONTROL
W
Reserved
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Description
UART Receive Data Register
UART Transmit Data Register
UART Status Register
Interrupt Mode Register
General Purpose Output 1 Register
General Purpose Output 2 Register
General Purpose Output 3 Register
General Purpose Output 4 Register
General Purpose Input 1 Register
General Purpose Input 2 Register
General Purpose Input 3 Register
General Purpose Input 4 Register
Interrupt Status Register
Pending Interrupt Register
Interrupt Enable Register
Interrupt Acknowledge Register
PIT1 Preload Register
PIT1 Counter Register
PIT1 Control Register
UART Programmable Baud Rate
PIT2 Preload Register
PIT2 Counter Register
PIT2 Control Register
PIT3 Preload Register
PIT3 Counter Register
PIT3 Control Register
PIT4 Preload Register
PIT4 Counter Register
PIT4 Control Register
Product Specification
13
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